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MX867P4

Low Power V.22 Modem

MX-COM Inc  

Low Power V.22 Modem

15

CMX867 Advance Information

4.9 Rx Data Register and USART

A flexible Rx USART is provided for all modem modes, meeting the requirements of V.14 for DPSK modems.

It can be programmed to treat the received data bit stream as Synchronous data or as Start-Stop characters.

In Synchronous mode the received data bits are all fed into the Rx Data Buffer which is copied into the C-BUS

Rx Data Register after every 8 bits.

In Start-Stop mode the USART Control logic looks for the start of each character, then feeds only the required

number of data bits (not parity) into the Rx Data Buffer. The parity bit (if used) and the presence of a Stop bit

are then checked and the data bits in the Rx Data Buffer copied to the C-BUS Rx Data Register.

b9

b7

b8

Status Register:

1010

Detector

(FSK only)

From FSK or

DPSK

Demodulator

Continuous

Unscrambled

1s detector

Continuous

Scrambled

1s detector

Descrambler

(DPSK only)

Enable

Continuous

0s detector

C-BUS Interface

Rx data

to µC

Rx Data Register

7

0

Rx Data Buffer

Parity bit checker

Rx USART

Start/Stop bits

USART Control

Bit rate clock

Figure 13: Rx Modem Data Paths

Whenever a new character is copied into the C-BUS Rx Data Register, the Rx Data Ready flag bit of the

Status Register is set to ‘1’ to prompt the µC to read the new data; and in Start-Stop mode, the Even Rx

Parity flag bit of the Status Register is updated.

In Start-Stop mode, if the Stop bit is missing (received as a ‘0’ instead of a ‘1’) the received character will still

be placed into the Rx Data Register and the Rx Data Ready flag bit set, but, unless allowed by the

V.14 overspeed option described below, the Status Register Rx Framing Error bit will also be set to ‘1’ and

the USART will re-synchronize onto the next ‘1’ – ‘0’ (Stop – Start) transition. The Rx Framing Error bit will

remain set until the next character has been received.

Rx Signal:

Start B0 B1

B7 Par'y Stop

Rx Data Ready flag bit:

Figure 14: Rx USART Function (Start-Stop mode, 8 Data Bits + Parity)

If the µC has not read the previous data from the Rx Data Register by the time that new data is copied to it

from the Rx Data Buffer then the Rx Data Overflow flag bit of the Status Register will be set to 1.

The Rx Data Ready flag and Rx Data Overflow bits are cleared to 0 when the Rx Data Register is read by the

µC.

For DPSK Start-Stop modes, V.14 requires that the receive USART be able to cope with missing Stop bits; up

to 1 missing Stop bit in every 8 consecutive received characters being allowed for the +1% overspeed (basic

signaling rate) V.14 mode and 1 in 4 for the +2.3% overspeed (extended signaling rate) mode.

To accommodate the requirements of V.14, the CMX867 Rx Mode Register can be set for 0, +1% or +2.3%

overspeed operation in DPSK Start-Stop modes. Missing Stop bits beyond those allowed by the selected

overspeed option will set the Rx Framing Error flag bit of the Status Register.

2000 MX-COM, Inc.

www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054

Doc. # 20480219.001

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA

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