BR24C01A-W 查看數據表（PDF） - ROHM Semiconductor
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BR24C01A-W Datasheet PDF : 13 Pages
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Memory ICs
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
!Electrical characteristics
DC characteristics (unless otherwise noted, Ta = −40 to + 85 °C, VCC = 2.7 to 5.5V)
Parameter
Symbol Min. Typ. Max. Unit
Input high level voltage
VIH
0.7VCC
−
−
V
Input low level voltage
VIL
−
−
0.3VCC
V
Output low level coltage
VOL
−
−
0.4
V
Input leakage current
ILI
−1
−
1
µA
Output leakage current
ILO
−1
−
1
µA
operatingcurrent dissipation
ICC
−
−
2.0
mA
Standby current
ISB
−
−
2.0
µA
Not designed for radiation resistance.
Conditions
−
−
IOL=3.0mA(SDA)
VIN=0V~VCC
VOUT=0V~VCC
VCC=5.5V, fSCL=400kHz
VCC=5.5V, SDA·SCL=VCC
A0, A1, A2=GND, WP=GND
Operating timing characteristics (unless otherwise noted, Ta = −40 to + 85 °C, VCC = 2.7 to 5.5V)
Parameter
Vcc=5V±10%
Vcc=3V±10%
Symbol
Unit
Min. Typ. Max. Min. Typ. Max.
SCL frequency
fSCL
−
− 400 −
− 100 kHz
Data clock HIGH time
tHIGH
0.6 −
− 4.0 −
−
µs
Data clock LOW time
tLOW
1.2 −
− 4.7 −
−
µs
SDA / SCL rise time
tR
−
− 0.3 −
− 1.0
µs
SDA / SCL fall time
tF
−
− 0.3 −
− 0.3
µs
Start condition hold time
tHD : STA 0.6
−
− 4.0 −
−
µs
Start condition setup time
tSU : STA 0.6
−
− 4.7 −
−
µs
Input data hold time
tHD : DAT
0
−
−
0
−
−
ns
Input data setup time
tSU : DAT 100 −
− 250 −
−
ns
Output data delay time
tPD
0.1 − 0.9 0.2 − 3.5
µs
Output data hold time
tDH
0.1 −
− 0.2 −
−
µs
Stop condition setup time
tSU : STO 0.6
−
− 4.7 −
−
µs
Bus open time before start of transfer
tBUF
1.2 −
− 4.7 −
−
µs
Internal write cycle time
tWR
−
−
10
−
−
10
ms
Noise erase valid time (SCL / SDA pins)
tI
−
− 0.05 −
− 0.1
µs
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