LPC8N04 查看數據表（PDF） - NXP Semiconductors.
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LPC8N04
NXP Semiconductors.
LPC8N04 Datasheet PDF : 39 Pages
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NXP Semiconductors
LPC8N04
32-bit ARM Cortex-M0+ microcontroller
8.4 Power management
The Power Management Unit (PMU) controls the switching between available power
sources and the powering of the different voltage domains in the IC.
8.4.1 System power architecture
The LPC8N04 accepts power from two different sources: from the external power supply
pin VDDBAT, or from the built-in NFC/RFID rectifier.
The LPC8N04 has a small automatic source selector that monitors the power inputs
(VBAT and VNFC, see Figure 5) as well as pin RESETN. The PSWBAT switch is kept
open until a trigger is given on pin RESETN or via the NFC field. If the trigger is given, the
always-on domain, VDD_ALON, itself is powered via the PSWBAT or the PSWNFC
switch: via VBAT, if VBAT > 1.72 V, or VNFC. Priority is given to VBAT when both VBAT
and VNFC are present.
The automatic source selector unit in the PMU decides on the powering of the internal
domains based on the power source.
• If a voltage > 1.72 V is detected on VBAT and not VNFC, VBAT powers the internal
domains after a trigger on pin RESETN or via NFC.
• If a voltage 1.72 V is detected on VBAT, and a higher voltage is detected on VNFC,
the internal domains are powered from VNFC.
• If a voltage > 1.72 V is detected at both VBAT and VNFC, the internal domains are
powered from VBAT.
• Switch over between power sources is possible. If initially both VBAT and VNFC are
available, the system is powered from VBAT. If VBAT then becomes unavailable
(because it is switched off externally, or by a PSWBAT/PSWNFC power switch
override), the internal domains are immediately powered from VNFC. Switch over is
supported in both directions.
• The user can force the selection of the VBAT input by disabling the automatic power
switch, which disables the automatic source selector voltage comparator.
When on NFC power only (passive operation), connecting one or more 100 nF external
capacitors in parallel to a GPIO pad, and setting that pad as an output driven to logic 1, is
advised. Preferably a high-drive pin should be chosen and several pins can be connected
in parallel.
PSWNFC and PSWBAT are the power switches. PSWNFC connects power to the
VDD_ALON power net when an RF field is present. PSWBAT connects power from the
battery when a positive edge is detected on RESETN. If no RF power is available, the
PMU can open this PSWBAT switch, effectively switching off the device. After connecting
VDDBAT to a power source, the PSWBAT switch is open until a rising edge is detected on
RESETN or RF power is applied.
Each component of the LPC8N04 resides in one of several internal power domains, as
indicated in Figure 5. The domains are VBAT, VNFC, VDD_ALON, VDD1V2 and
VDD1V6. The domains VDD_ALON, VDD1V2 and VDD1V6 are powered, or not,
depending on the mode of the LPC8N04. There are five modes: active, sleep, deep sleep,
deep power-down and battery off.
LPC8N04
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.3 — 15 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
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