LPC8N04 查看數據表（PDF） - NXP Semiconductors.
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LPC8N04
NXP Semiconductors.
LPC8N04 Datasheet PDF : 39 Pages
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NXP Semiconductors
LPC8N04
32-bit ARM Cortex-M0+ microcontroller
8. Functional description
8.1 ARM Cortex-M0+ core
Refer to the Cortex-M0+ Devices Technical Reference Manual (Ref. 1) for a detailed
description of the ARM Cortex-M0+ processor.
The LPC8N04 ARM Cortex-M0+ core has the following configuration:
• System options
– Nested Vectored Interrupt Controller (NVIC)
– Fast (single-cycle) multiplier
– System tick timer
– Support for wake-up interrupt controller
– Vector table remapping register
– Reset of all registers
• Debug options
– Serial Wire Debug (SWD) with two watchpoint comparators and four breakpoint
comparators
– Halting debug is supported
8.2 Memory map
Figure 3 shows the memory and peripheral address space of the LPC8N04.
The only AHB peripheral device on the LPC8N04 is the GPIO module. The APB
peripheral area is 512 kB in size. Each peripheral is allocated 16 kB of space.
All peripheral register addresses are 32-bit word aligned. Byte and half-word addressing is
not possible. All reading and writing are done per full word.
LPC8N04
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.3 — 15 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
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