ICS83940BY 查看數據表（PDF） - Integrated Circuit Systems
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ICS83940BY Datasheet PDF : 12 Pages
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Integrated
Circuit
Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83940 is a low skew, 1-to-18 LVPECL-
,&6
to-LVCMOS Fanout Buffer and a member of the
HiPerClockS™ HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS83940 has two
selectable clock inputs. The PCLK, nPCLK pair
can accept LVPECL, CML, or SSTL input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS outputs are designed to drive
50Ω series or parallel terminated transmission lines.
The ICS83940 is characterized at full 3.3V, full 2.5V and mixed
3.3V input and 2.5V output operating supply modes. Guaran-
teed output and part-to-part skew characteristics make the
ICS83940 ideal for those clock distribution applications de-
manding well defined performance and repeatability.
FEATURES
• 18 LVCMOS outputs, 23Ω typical output impedance
• Selectable LVCMOS_CLK or LVPECL clock inputs
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Part to part skew: 750ps (maximum)
• Full 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Pin compatible with the MPC940L
BLOCK DIAGRAM
CLK_SEL
PCLK
nPCLK
0
LVCMOS_CLK
1
PIN ASSIGNMENT
18
Q0:Q17
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
VDD
VDDO
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
ICS83940 21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
Q6
Q7
Q8
VDD
Q9
Q10
Q11
GND
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Pacakge
Top View
83940BY
www.icst.com/products/hiperclocks.html
1
REV. A APRIL 15, 2002
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