SY100EL91L 查看數據表（PDF） - Micrel
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SY100EL91L Datasheet PDF : 5 Pages
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3.3V TRIPLE LVPECL-to-ECL
OR LVPECL-to-LVECL
TRANSLATOR
SY100EL91L
FINAL
FEATURES
s 3.3V power supply
s 620ps propagation delay
s Fully differential design
s Supports low voltage operation
s Available in 20-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
VCC 1
D0 2
D0 3
PECL_VBB 4
D1 5
D1 6
PECL_VBB 7
D2 8
D2 9
VEE 10
20 VCC
19 Q0
18 Q0
17 GND
16 Q1
15 Q1
14 GND
13 Q2
12 Q2
11 VCC
SOIC
TOP VIEW
DESCRIPTION
The SY100EL91L is a triple LVPECL-to-ECL or
LVPECL-to-LVECL translator.
A VBB output is provided for interfacing with single
ended PECL signals at the input. If a single ended input
is to be used, the VBB output should be connected to the
D input. The active signal would then drive the D input.
When used, the VBB output should be bypassed to ground
via a 0.01µF capacitor. The VBB output is designed to act
as the switching reference for the EL91L under single
ended input switching conditions. As a result this pin can
only source/sink up to 0.5mA of current.
To accomplish the level translation the EL91L requires
three power rails. The VCC supply should be connected
to the positive supply, and the VEE pin should be
connected to the negative power supply. The GND pins
as expected are connected to the system ground plane.
Both VEE and VCC should be bypassed to ground via
0.01µF capacitors.
Under open input conditions, the D input will be biased
at VCC/2 and the D input will be pulled to GND. This
condition will force the Q output to a LOW, ensuring
stability.
PIN NAMES
Pin
Dn
Qn
PECL_VBB
Function
PECL Inputs
ECL Outputs
PECL Reference Voltage Output
FUNCTION TABLE
Function
LVPECL-to-ECL
LVPECL-to-LVECL
Vcc
3.3V
3.3V
VEE
–5.0V
–3.3V
Rev.: F
Amendment: /2
1
Issue Date: November, 1999
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