AD5301 查看數據表（PDF） - Analog Devices

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AD5301

2.5 V to 5.5 V, 120 μ
A, 2-Wire Interface, Voltage Output 8-/10-/12-Bit DACs

Analog Devices 

AD5301/AD5311/AD5321

Write Operation

When writing to the AD5301/AD5311/AD5321 DACs, the user

must begin with an address byte, after which the DAC will

acknowledge that it is prepared to receive data by pulling SDA

low. This address byte is followed by the 16-bit word in the

form of two control bytes. The write operations for the three

DACs are shown in the figures below.

SCL

SDA

0

START

COND

BY

MASTER

SCL

0

0

1

1

ADDRESS BYTE

A1* A0 R/W

X

ACK

BY

AD5301

X PD1 PD0 D7 D6 D5

MOST SIGNIFICANT CONTROL BYTE

D4

ACK

BY

AD5301

SDA

D3 D2 D1 D0

X

X

X

LEAST SIGNIFICANT CONTROL BYTE

*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.

X

ACK STOP

BY COND

AD5301 BY

MASTER

Figure 24. AD5301 Write Sequence

SCL

SDA

0

START

COND

BY

MASTER

SCL

0

0

1

1

ADDRESS BYTE

A1* A0 R/W

X

ACK

BY

AD5311

X PD1 PD0 D9 D8 D7

MOST SIGNIFICANT CONTROL BYTE

D6

ACK

BY

AD5311

SDA

D5 D4 D3 D2 D1 D0

X

LEAST SIGNIFICANT CONTROL BYTE

*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.

X

ACK STOP

BY COND

AD5311 BY

MASTER

Figure 25. AD5311 Write Sequence

SCL

SDA

0

START

COND

BY

MASTER

SCL

0

0

1

1

ADDRESS BYTE

A1* A0 R/W

X

ACK

BY

AD5321

X PD1 PD0 D11 D10 D9

MOST SIGNIFICANT CONTROL BYTE

D8

ACK

BY

AD5321

SDA

D7 D6 D5 D4 D3 D2 D1

LEAST SIGNIFICANT CONTROL BYTE

*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.

D0

ACK STOP

BY COND

AD5321 BY

MASTER

Figure 26. AD5321 Write Sequence

REV. A

–11–

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