MK10FN1M0ZVLQ10 查看數據表（PDF） - NXP Semiconductors.

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MK10FN1M0ZVLQ10

K10 Sub-Family

NXP Semiconductors. 

General

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be

recognized in that case.

2. The greater synchronous and asynchronous timing must be met.

3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and

VLLSx modes.

4. 75 pF load

5. 15 pF load

5.4 Thermal specifications

5.4.1 Thermal operating requirements

Table 11. Thermal operating requirements

Symbol

TJ

TA

Description

Die junction temperature

Ambient temperature

Min.

Max.

Unit

–40

125

°C

–40

105

°C

5.4.2 Thermal attributes

Board type

Single-layer (1s)

Symbol

RθJA

Four-layer (2s2p) RθJA

Single-layer (1s) RθJMA

Four-layer (2s2p) RθJMA

—

RθJB

—

RθJC

Description

80 LQFP

Thermal

50

resistance, junction

to ambient (natural

convection)

Thermal

35

resistance, junction

to ambient (natural

convection)

Thermal

39

resistance, junction

to ambient (200 ft./

min. air speed)

Thermal

29

resistance, junction

to ambient (200 ft./

min. air speed)

Thermal

19

resistance, junction

to board

Thermal

8

resistance, junction

to case

Table continues on the next page...

Unit

°C/W

°C/W

°C/W

°C/W

°C/W

°C/W

Freescale Semiconductor, Inc.

K10 Sub-Family Data Sheet, Rev. 3, 6/2013.

Notes

1

1

1

1

2

3

21

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