7C1338-50 查看數據表（PDF） - Cypress Semiconductor

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产品描述 (功能)

生产厂家

7C1338-50

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Cypress Semiconductor 

Timing Diagrams (continued)

Read/Write Cycle Timing

CY7C1338

CLK

tCH

tCYC

tCL

ADD

tAS

A

ADSP

tADS

ADSC

tAH

B

tADS

C

D

tADH

tADH

ADV

tADVS

tADVH

CE1

CE

tCES

tCES

tCEH

tCEH

WE

tWES

tWEH

ADSP ignored

OE

with CE1 HIGH

tCLZ

Data

In/Out

tCDV

Q(A)

Q(B)

Q

Q

(B+1) (B+2)

Q

(B+3)

Q(B)

tEOHZ

D(C)

D

D

D

(C+1) (C+2) (C+3)

tDOH

tCHZ

Q(D)

Device originally

deselected

WE is the combination of BWE, BWS[1:0], and GW to define a write cycle (see Write Cycle Descriptions table).

CE is the combination of CE2 and CE3. All chip selects need to be active in order to select

the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,

Qx stands for Data-out X.

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