CS61574A-IP1 查看數據表（PDF） - Cirrus Logic
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CS61574A-IP1 Datasheet PDF : 44 Pages
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CS61574A CS61575
Application
RX:
T1 & E1
Turns
Ratio(s)
1:2CT
TX:
1:1.15
T1
TX:
1:1.26
E1 (75 & 120 Ω) 1:1
RX &TX:
T1
RX &TX:
E1 (75 & 120 Ω)
RX &TX:
T1
RX &TX:
E1 (75 & 120 Ω)
RX :
T1 & E1
TX:
E1 (75 & 120 Ω)
1:2CT
1:1.15
1:2CT
1:1.26
1:1
1:2CT
1:1.15
1:2CT
1:1.26
1:1
1:2CT
1:1.26
1:1
Manufacturer
Pulse Engineering
Schott
Bel Fuse
Pulse Engineering
Schott
Bel Fuse
Pulse Engineering
Schott
Bel Fuse
Pulse Engineering
Bel Fuse
Pulse Engineering
Bel Fuse
Pulse Engineering
Bel Fuse
Pulse Engineering
Bel Fuse
Pulse Engineering
Pulse Engineering
Part Number
Package Type
PE-65351
67129300
0553-0013-HC
PE-65388
67129310
0553-0013-RC
PE-65389
67129320
0553-0013-SC
PE-65565
0553-0013-7J
PE-65566
0553-0013-8J
1.5 kV through-hole, single
1.5 kV through-hole, single
1.5 kV through-hole, single
1.5 kV through-hole, dual
1.5 kV through-hole, dual
PE-65765
S553-0013-06
PE-65766
S553-0013-07
1.5 kVsurface-mount, dual
1.5 kV surface-mount, dual
PE-65835
PE-65839
3 kV through-hole, single
EN60950, EN41003 approved
3 kV through-hole, single
EN60950, EN41003 approved
Table A3. Recommended Transformers
Interfacing The CS61575 and CS61574A With
the CS62180B T1 Transceiver
To interface with the CS62180B, connect the de-
vices as shown in Figure A4. In this case, the line
interface and CS62180B are in Host Mode con-
trolled by a microprocessor serial interface. If the
line interface is used in Hardware Mode, then the
line interface RCLK output must be inverted be-
fore being input to the CS62180B. If the
CS61575 or CS61574A is used in Extended
Hardware Mode, the RCLK output does not have
to be inverted before being input to the
CS62180B.
TO HOST CONTROLLER
SCLK
SDO
SDI
CS
TCLK
TPOS
TNEG
1.544 MHz
CLOCK
SIGNAL
RNEG
RPOS
RCLK
ACLK
TCLK
TPOS
TNEG
RNEG
RPOS
RCLK
SCLK
SDO
SDI
CS
INT
CLKE
MODE
V+
100k
22k V+
CS62180B
CS61574A OR
CS61575
Figure A4. Interfacing the CS61574A or CS61575
with a CS62180B (Host Mode)
DS154F2
31
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