CDB53L32A 查看數據表（PDF） - Cirrus Logic

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CDB53L32A

Low Voltage, Stereo A/D Converter

Cirrus Logic 

CS53L32A

SCLK

LRCK

t sclkl

t sclkh

t slrd

SDOUT

t dss

MSB

Figure 1. SCLK to LRCK and SDOUT, Slave Mode

t sclkw

SCLK

LRCK

SDOUT

t slrd

t sdo

MSB

MSB-1

Figure 2. SCLK to LRCK and SDOUT, Master Mode

LRCK Input

6 ns

10 ns

MCLK Input

No rising edge of MCLK allowed within this

timing window.

Figure 3. Relationship Required Between LRCK and MCLK in Slave Mode

DS513F1

11

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