CXP81960 查看數據表（PDF） - Sony Semiconductor
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CXP81960 Datasheet PDF : 27 Pages
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CXP81952/81960
(5) Interruption, reset input
Item
External interruption
high and low level widths
Reset input low level width
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)
Symbol Pins Conditions Min. Max. Unit
INT0
tIH
tIL
INT1
INT2
NMI
PJ0 to PJ7
tRSL
RST
1
µs
32/fc
µs
Fig. 8. Interruption input timing
INT0
INT1
INT2
NMI
PJ0 to PJ7
(During standby release input)
(Falling edge)
tIH
0.8VDD
tIL
0.2VDD
Fig. 9. Reset input timing
tRSL
RST
0.2VDD
(6) Others
Item
EXI input
high and low level widths
Symbol
tEIH
tEIL
Pins
EXI0
EXI1
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)
Conditions
Min.
Max. Unit
tsys = 2000/fc
tFRC × 8 + 200 + tsys
ns
Note) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
tFRC = 1000/fc [ns]
Fig. 10. Other timings
tEIH
tEIL
EXI0
EXI1
0.8VDD
0.2VDD
– 24 –
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