HI5660/6IB 查看數據表（PDF） - Intersil
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HI5660/6IB Datasheet PDF : 11 Pages
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Timing Diagrams
HI5660
CLK
50%
D7-D0
IOUT
1/2 LSB ERROR BAND
tSETT
tPD
FIGURE 1. OUTPUT SETTLING TIME DIAGRAM
V
GLITCH AREA = 1/2 (H x W)
HEIGHT (H)
WIDTH (W)
t (ps)
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
CLK
D7-D0
IOUT
tPW1
tPW2
tSU
tSU
tSU
tHLD
tHLD
tHLD
50%
tPD
tSETT
tPD
tSETT
tPD
tSETT
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
6
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