AT89C51CC03C-7CTIM 查看數據表（PDF） - Atmel Corporation

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AT89C51CC03C-7CTIM

Enhanced 8-bit MCU with CAN Controller and Flash Memory

Atmel Corporation 

Port 0 and Port 2

AT89C51CC03

Figure 1. Port 1, Port 3 and Port 4 Structure

READ

LATCH

INTERNAL

BUS

WRITE

TO

LATCH

D P1.X Q

P3.X

P4.X

LATCH

CL

ALTERNATE

OUTPUT

FUNCTION

VCC

INTERNAL

PULL-UP (1)

P1.x

P3.x

P4.x

READ

PIN

ALTERNATE

INPUT

FUNCTION

Note: The internal pull-up can be disabled on P1 when analog function is selected.

Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port

0, shown in Figure 3, differs from the other Ports in not having internal pull-ups. Figure 3

shows the structure of Port 2. An external source can pull a Port 2 pin low.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-

ister (x = 0 or 2). To use a pin for general-purpose input, set the bit in the Px register to

turn off the output driver FET.

Figure 2. Port 0 Structure

ADDRESS LOW/

DATA

CONTROL

READ

LATCH

1

INTERNAL

BUS

D

Q

0

P0.X

WRITE

TO

LATCH

LATCH

VDD

(2)

P0.x (1)

READ

PIN

Notes:

1. Port 0 is precluded from use as general-purpose I/O Ports when used as

address/data bus drivers.

2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only.

Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain.

9

4182K–CAN–05/06

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