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AAT1149

3MHz Fast Transient 400mA Step-Down Converter

Advanced Analogic Technologies 

SwitchRegTM

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AAT1149

3MHz Fast Transient 400mA Step-Down Converter

Thermal Calculations

There are three types of losses associated with the

AAT1149 step-down converter: switching losses, conduc-

tion losses, and quiescent current losses. Conduction

losses are associated with the RDS(ON) characteristics of the

power output switching devices. Switching losses are

dominated by the gate charge of the power output switch-

ing devices. At full load, assuming continuous conduction

mode (CCM), a simplified form of the losses is given by:

PTOTAL =

IO2 · (RDS(ON)H · VO + RDS(ON)L · [VIN - VO])

VIN

+ (tsw · FS · IO + IQ) · VIN

IQ is the step-down converter quiescent current. The

term tsw is used to estimate the full load step-down con-

verter switching losses.

For the condition where the step-down converter is in

dropout at 100% duty cycle, the total device dissipation

reduces to:

PTOTAL = IO2 · RDS(ON)H + IQ · VIN

Since RDS(ON), quiescent current, and switching losses all

vary with input voltage, the total losses should be inves-

tigated over the complete input voltage range.

Given the total losses, the maximum junction tempera-

ture can be derived from the θJA for the SC70JW-8 pack-

age which is 160°C/W.

TJ(MAX) = PTOTAL · ΘJA + TAMB

1. The input capacitor (C2) should connect as closely as

possible to IN (Pin 3) and PGND (Pins 6-8).

2. C1 and L1 should be connected as closely as possi-

ble. The connection of L1 to the LX pin should be as

short as possible.

3. The feedback trace or FB pin (Pin 2) should be sepa-

ate from any power trace and connect as closely as

possible to the load point. Sensing along a high-

current load trace will degrade DC load regulation. If

external feedback resistors are used, they should be

placed as closely as possible to the FB pin (Pin 2) to

minimize the length of the high impedance feedback

trace.

4. The resistance of the trace from the load return to

the PGND (Pins 6-8) should be kept to a minimum.

This will help to minimize any error in DC regulation

due to differences in the potential of the internal

signal ground and the power ground.

5. The pad on the PCB for the WLCSP-5 package should

use NSMD (non-solder mask defined) configuration

due to its tighter control on the copper etch process.

A pad thickness of less than 1oz is recommended to

achieve higher stand-off. A high density, small foot-

print layout can be achieved using an inexpensive,

miniature, non-shielded, high DCR inductor, as

shown in Figure 8.

WLCSP Package Light Sensitivity

The electrical performance of the WLCSP package can be

adversely affected by exposing the device to certain light

sources such as direct sunlight or a halogen lamp whose

wavelengths are red and infra-reds. However, fluores-

cent lighting has very little effect on the electrical perfor-

mance of the WLCSP package.

Layout

The suggested PCB layout for the AAT1149 is shown in

Figures 1, 2, and 3. The following guidelines should be

used to help ensure a proper layout.

Figure 8: Minimum Footprint Evaluation Board

Using 2.0x1.25x1.0mm Inductor.

16

www.analogictech.com

1149.2008.08.1.3

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