IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKB
CSB
W/RB
MBB
ENB
B0-B35
tENS1
tENS1
tENS2
tENS2
tENH
tENH
tENH
tENH
tDS
tDH
W1
CLKA
MBF2
tPMF
CSA
W/RA
MBA
ENA
A0-A35
tEN
tPMR
tMDV
FIFO2 Output Register
COMMERCIAL TEMPERATURE RANGE
tPMF
tENS2
tENH
tDIS
W1 (Remains valid in Mail 2 Register after read)
4660 drw23
Figure 21. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
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