DS2182 查看數據表（PDF） - Maxim Integrated

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DS2182

T1 Line Monitor Chip

Maxim Integrated 

Figure 6. Alarm Output Timing

DS2182A T1 Line Monitor Chip

NOTE 1: RFER TRANSITIONS HIGH DURING F-BIT TIME IF RECEIVED FRAMING PATTERN BIT IS IN ERROR.

(FRAME 12 F-BITS IN 193S ARE IGNORED IF RCR2.3 = 1.) ALSO, IN 193E, RFER TRANSITIONS HIGH ONE-

HALF BIT-TIME BEFORE RISING EDGE OF RMSYNC TO INDICATE A CRC6 ERROR FOR THE PREVIOUS

MULTIFRAME.

NOTE 2: RBV INDICATES RECEIVED BIPOLAR VIOLATION AND TRANSITIONS HIGH WHEN ACCUSED BIT

EMERGES FROM RSER. IF B8ZS IS ENABLED, RBV DOES NOT REPORT THE ZERO REPLACEMENT

CODE.

NOTE 3: RCL TRANSITIONS HIGH WHEN 192 CONSECUTIVE BITS ARE 0; RCL TRANSITIONS LOW UPON

RECEPTION OF 12.5% 1’S DENSITY.

NOTE 4: RLOS TRANSITIONS HIGH DURING F-BIT TIME THAT CAUSED AN OOF EVENT IF AUTO-RESYNC IS

ENABLED (RCR1.1 = 0). RESYNC ALSO OCCURS WHEN LOSS-OF-CARRIER IS DETECTED (RCL = 1) IF

RCR1.7 = 0. WHEN RCR1.1 = 1, RLOS REMAINS LOW UNTIL RESYNC OCCURS, REGARDLESS OF OOF

OR CARRIER LOSS FLAGS. IN THIS SITUATION, RESYNC IS INITIATED ONLY WHEN RCR1.0

TRANSITIONS LOW-TO-HIGH OR THE RST PIN TRANSITIONS HIGH-LOW-HIGH.

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