DS2182 查看數據表（PDF） - Maxim Integrated

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DS2182

T1 Line Monitor Chip

Maxim Integrated 

DS2182A T1 Line Monitor Chip

Table 1. Pin Description

PIN

NAME

TYPE

FUNCTION

1

INT

O

Receive Alarm Interrupt. Flags host controller during alarm conditions. Active

low; open-drain output.

2

SDI

I Serial Data In. Data for on-board registers. Sampled on rising edge of SCLK.

Serial Data Out. Control and status information from on-board registers.

3

SDO

O Updated on falling edge of SCLK; tri-stated during serial port write or when CS

is high.

4

CS

I Chip Select. Must be low to read or write the serial port.

5

6, 13

7

8

9

SCLK

N.C.

RYEL

RLINK

RLCLK

I Serial Data Clock. Used to read or write the serial port registers.

—

No Connect. No internal connection. This pin can be connected to either VSS

or VDD, or it can be floated.

O

Receive Yellow Alarm. Transitions high when a yellow alarm detected; goes

low when the alarm clears.

Receive Link Data. Updated with extracted FDL data one RCLK before start

O of odd frames (193E) and held until next update. Updated with extracted S-bit

data one RCLK before start of even frames (193S) and held until next update.

O Receive Link Clock. 4kHz demand clock for RLINK

10

RCLK

I Receive Clock. 1.544MHz primary clock

11

RCHCLK

O

Receive Channel Clock. 192kHz clock; identifies timeslot (channel)

boundaries

12

RSER

O

Receive Serial Data. Received NRZ serial data; updated on rising edges of

RCLK

15

RFSYNC

O

Receive Frame Sync. Extracted 8kHz clock, one RCLK wide; F-bit position in

each frame

16

RMSYNC

O

Receive Multiframe Sync. Extracted multiframe sync; positive-going edge

indicates start of multiframe; 50% duty cycle

Receive ABCD Signaling. Extracted signaling data output; valid for each

17

RABCD

O channel in signaling frames. In non-signaling frames, RABCD outputs the LSB

of each channel word.

18

RSIGFR

O

Receive Signaling Frame. High during signaling frames; low during non-

signaling frames (and during resync)

19

RSIGSEL

O

Receive Signaling Select. In 193E framing, a .667kHz clock that identifies

signaling frames A and C; a 1.33kHz clock in 193S

21

RST

I

Reset. A high-low transition clears all internal registers and resets counters. A

high-low-high transition initiates a resync.

22

RPOS

23

RNEG

I

Receive Bipolar Data Inputs. Sampled on falling of RCLK. Connect together

to receive NRZ data and disable bipolar violation monitoring circuitry.

24

RCL

25

RBV

O

Receive Carrier Loss. High if 192 consecutive 0’s appear at RPOS and

RNEG; goes low upon seeing 12.5% 1’s density.

O

Receive Bipolar Violation. High during accused bit time at RSER. If bipolar

violation detected, low otherwise.

26

RFER

O

Receive Frame Error. High during F-bit time when FT or FS errors occur

(193S), or when FPS or CRC errors occur (193E). Low during resync.

27

RLOS

O

Receive Loss-of-Sync. Indicates sync status; high when internal resync is in

progress, low otherwise.

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