DS3252N 查看數據表（PDF） - Maxim Integrated

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DS3252N

Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Maxim Integrated 

DS3251/DS3252/DS3253/DS3254

Table 6-G. Transmitter Data Select Options

TDSA TDSB E3M

STS

Tx

MODE

TRANSMIT DATA SELECTED

0

0

X

X

Any Normal data as input at TPOS and TNEG

0

1

0

0

DS3

0

1

1

0

E3 Unframed all ones

0

1

1

1

STS-1

0

1

0

1

DS3 DS3 AIS per ANSI T1.107 (Figure 9-2)

1

0

X

X

Any Unframed 100100… pattern

1

1

1

0

E3

223 - 1 PRBS pattern per ITU O.151

1

1

1

1

0

1

X

1

DS3

STS-1

215 - 1 PRBS pattern per ITU O.151

Note 1:

Note 2:

This coding of the TDSA, TDSB, E3M, and STS bits allows AIS generation to be enabled by

holding TDSA = 0 and changing TDSB from 0 to 1. The type of DS3 AIS signal is selected by the

STS bit with E3M = 0.

If E3M and/or STS are changed when {TDSA,TDSB} ≠ 00, TDSA and TDSB must both be cleared

to 0. After they are cleared, TDSA and TDSB can be configured to transmit a pattern in the new

operating mode.

Table 6-H. Receiver PRBS Pattern Select Options

E3M

STS

Rx

MODE

RECEIVER PRBS PATTERN

SELECTED

1

0

E3

223 - 1 PRBS pattern per ITU O.151

0

1

X

1

DS3

STS-1

215 - 1 PRBS pattern per ITU O.151

Table 6-I. Hardware Mode Jitter Attenuator Configuration

TJA

RJA

JITTER ATTENUATOR CONFIGURATION

0

0

Disabled

0

1

Receive path, 16-bit buffer depth

1

0

Transmit path, 16-bit buffer depth

1

1

Transmit path, 32-bit buffer depth

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