DS3252N 查看數據表（PDF） - Maxim Integrated

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DS3252N

Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Maxim Integrated 

Register Name:

Register Description:

Register Address:

SRIEn

Status Register Interrupt Enable

05h, 15h, 25h, 35h

Bit

Name

Default

7

JAFIE

0

6

JAEIE

0

5

TDMIE

0

4

PRBSIE

0

3

PBERIE

0

Bit 7: Jitter Attenuator Full Interrupt Enable (JAFIE)

0 = mask JAFL interrupt

1 = enable JAFL interrupt

Bit 6: Jitter Attenuator Empty Interrupt Enable (JAEIE)

0 = mask JAEL interrupt

1 = enable JAEL interrupt

Bit 5: Transmitter Driver Monitor Interrupt Enable (TDMIE)

0 = mask TDML interrupt

1 = enable TDML interrupt

Bit 4: PRBS Detector Interrupt Enable (PRBSIE)

0 = mask PRBSL interrupt

1 = enable PRBSL interrupt

Bit 3: PRBS Detector Bit-Error Interrupt Enable (PBERIE)

0 = mask PBERL interrupt

1 = enable PBERL interrupt

Bit 2: Receiver Line-Code Violation Interrupt Enable (RCVIE)

0 = mask RCVL interrupt

1 = enable RCVL interrupt

Bit 1: Receiver Loss-of-Clock Lock Interrupt Enable (RLOLIE)

0 = mask RLOLL interrupt

1 = enable RLOLL interrupt

Bit 0: Receiver Loss-of-Signal Interrupt Enable (RLOSIE)

0 = mask RLOSL interrupt

1 = enable RLOSL interrupt

DS3251/DS3252/DS3253/DS3254

2

RCVIE

0

1

RLOLIE

0

0

RLOSIE

0

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