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ISL6416 查看數據表(PDF) - Renesas Electronics

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ISL6416 Datasheet PDF : 11 Pages
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ISL6416
Pin Descriptions
VOUT1 - This pin is the output for LDO1. Bypass with a
minimum of 2.2µF, low ESR ceramic capacitor to GND for
stable operation.
VIN - Supply input pins. Connect to input power source.
Bypass with a minimum 2.2µF capacitor to GND. Both VIN
pins must be tied together on the PC board, close to the IC.
GND - Ground for LDO1, LDO2, and LDO3.
CC1 - Compensation Capacitor for LDO1. Connect a
0.033µF capacitor from CC1 to GND.
SHDN - Shutdown input for all LDOs. This pin is pulled up
internally. Drive this pin LOW to turn off all LDOs.
VOUT2 - This pin is the output for LDO2. Bypass with a
minimum of 2.2µF, low ESR capacitor to GND for stable
operation.
CT - Timing pin for the RESET circuit pulse width. A
capacitor connected from this pin to GND will set a delay the
RESET delay. Leaving this pin open will make the RESET
delay approximately zero.
CC2 - Compensation capacitor for LDO2. Connect a
0.033µF capacitor from CC2 to GND.
VOUT3 - This pin is output for LDO3. Bypass with a
minimum of 2.2µF, low ESR capacitor to GND3 for stable
operation.
CC3 - Compensation capacitor for LDO3. Connect a
0.033µF capacitor from CC3 to GND3.
FAULT - This is the power good indicator for LDO1. When
the 1.8V output is out of regulation this pin goes LOW. This
pin also goes LOW during thermal shutdown or an
overcurrent event on LDO1. Leave floating if not used.
RESET - This pin is the active-LOW output of the push-pull
output stage of the integrated reset supervisory circuit. The
reset circuit monitors VIN and asserts a RESET output at this
pin, if VIN falls below the reset threshold. The RESET output
remains LOW, while the VIN pin voltage is below the reset
threshold, and for a time set by the CT capacitor, after VIN
rises above the reset threshold.
Functional Description
The ISL6416 is a 3-in-1 multi-output, low dropout, regulator
designed for wireless chipset power applications. It supplies
three fixed output voltages 1.8V, 2.8V and 2.8V. Each LDO
consists of a 1.2V reference, error amplifier, MOSFET driver,
P-Channel pass transistor, dual-mode comparator and
internal feedback voltage divider.
The 1.2V band gap reference is connected to the error
amplifier’s non-inverting input. The error amplifier compares
this reference to the selected feedback voltage and amplifies
the difference. The MOSFET driver reads the error signal
FN9193 Rev 0.00
Nov 3, 2004
and applies the appropriate drive to the P-Channel pass
transistor. If the feedback voltage is lower then the reference
voltage, the pass transistor gate is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the
pass transistor gate is driven higher, allowing less current to
pass to the output. The output voltage is fed back through an
internal resistor divider connected to OUT1/2/3 pins.
Additional blocks include an output overcurrent protection,
thermal sensor, fault detector, RESET function and
shutdown logic.
Internal P-Channel Pass Transistors
The ISL6416 features a typical 0.5rDS(ON) P-channel
MOSFET pass transistor. This provides several advantages
over similar designs using PNP bipolar pass transistors. The
P-Channel MOSFET requires no base drive, which reduces
quiescent current considerably. PNP based regulators waste
considerable current in dropout when the pass transistor
saturates. They also use high base drive currents under
large loads. The ISL6416 does not suffer from these
problems.
Integrated Reset for MAC/ Baseband Processors
The ISL6416 includes a microprocessor supervisory block.
This block eliminates the extra reset IC and external
components needed in wireless chipset applications. This
block performs a single function; it asserts a RESET signal
whenever the VIN supply voltage decreases below a preset
threshold, keeping it asserted for a programmable time (set
by external capacitor CT) after the VIN pin voltage has risen
above the reset threshold. The reset threshold for the
ISL6416 is 2.63V typical.
The voltage at the CT pin is compared to the 1.2V bandgap
voltage. The charging of the CT capacitor behaves like an
RC network and the RESET delay can be approximated by:
Td = -R*C*ln(1-1.2V/VIN)
Where C is the capacitor at CT, and R is 11.1Mfor
VIN = 3.3V. With no capacitor on the CT pin the RESET
delay will be close to zero. Figure 12 shows the RESET
delay vs CT capacitance.
500
400
300
200
100
0
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0
CT (µF)
FIGURE 12. RESET DELAY vs CT CAPACITANCE
Page 8 of 11

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