P89LPC915 查看數據表（PDF） - NXP Semiconductors.

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P89LPC915

8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converter

NXP Semiconductors. 

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

Table 6. P89LPC917 pin description …continued

Symbol

Pin

Type Description

P0.7/T1/KBI7/CLKOUT

11

I/O P0.7 — Port 0 bit 7.

I/O T1 — Timer/counter 1 external count input or overflow output.

I

KBI7 — Keyboard input 7.

O CLKOUT — Clock output.

P1.0 to P1.5

I/O, I

[1]

Port 1: Port 1 is a 6-bit I/O port with a user-configurable output type,

except for three pins as noted below. During reset Port 1 latches are

configured in the input only mode with the internal pull-up disabled. The

operation of the configurable Port 1 pins as inputs and outputs depends

upon the port configuration selected. Each of the configurable port pins

are programmed independently. Refer to Section 8.13.1 “Port

configurations” and Table 15 “Static characteristics” for details. P1.2 to

P1.3 are open drain when used as outputs. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

P1.0/TXD

10

I/O P1.0 — Port 1 bit 0.

O TXD — Transmitter output for serial port.

P1.1/RXD

9

I/O P1.1 — Port 1 bit 1.

I

RXD — Receiver input for serial port.

P1.2/T0/SCL

8

I/O P1.2 — Port 1 bit 2 (open-drain when used as output).

I/O T0 — Timer/counter 0 external count input or overflow output (open-drain

when used as output).

I/O SCL — I2C serial clock input/output.

P1.3/INT0/SDA

7

I/O P1.3 — Port 1 bit 3 (open-drain when used as output).

I

INT0 — External interrupt 0 input.

I/O SDA — I2C serial data input/output.

P1.4/INT1

6

I

P1.4 — Port 1 bit 4.

I

INT1 — External interrupt 1 input.

P1.5/RST

3

I

P1.5 — Port 1 bit 5 (input only).

I

RST — External Reset input during power-on or if selected via UCFG1.

When functioning as a reset input, a LOW on this pin resets the

microcontroller, causing I/O ports and peripherals to take on their default

states, and the processor begins execution at address 0. Also used

during a power-on sequence to force ISP mode. When using an

oscillator frequency above 12 MHz, the reset input function of P1.5

must be enabled. An external circuit is required to hold the device in

reset at power-up until VDD has reached its specified level. When

system power is removed VDD will fall below the minimum specified

operating voltage. When using an oscillator frequency above

12 MHz, in some applications, an external brownout detect circuit

may be required to hold the device in reset when VDD falls below the

minimum specified operating voltage.

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

© NXP B.V. 2009. All rights reserved.

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