EVAL-ADF4113EB2 查看數據表（PDF） - Analog Devices
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EVAL-ADF4113EB2 Datasheet PDF : 28 Pages
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ADF4110/ADF4111/ADF4112/ADF4113
TIMING CHARACTERISTICS
Guaranteed by design but not production tested. AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP ≤ 6 V;
AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
Limit at TMIN to TMAX (B Version)
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
CLOCK
DATA
DB20 (MSB)
t1
t2
DB19
LE
t3
t4
DB2
DB1
(CONTROL BIT C2)
LE
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t6
t5
Rev. C | Page 5 of 28
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