ADV7403BSTZ-110 查看數據表（PDF） - Analog Devices

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ADV7403BSTZ-110

12-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer

Analog Devices 

Data Sheet

Timing Diagram

t3

SDA1/SDA2

t5

t3

SCLK1/SCLK2

t6

t1

t2

t7

t4

t8

Figure 2. I2C Timing

LLC1

t9

t10

P0 TO P29, VS, HS,

FIELD/DE,

SFL/SYNC_OUT

t11

t12

Figure 3. Pixel Port and Control SDR Output Timing (SD Core)

LLC1

t9

t10

t13

t14

P0 TO P29, VS,

HS, FIELD/DE

Figure 4. Pixel Port and Control SDR Output Timing (CP Core)

LLC1

P6 TO P9,

P10 TO P19

t16

t15

t18

t17

Figure 5. Pixel Port and Control DDR Output Timing (CP Core)

DCLK_IN

CONTROL

INPUTS

HS_IN

VS_IN

DE_IN

P0 TO P1, P10 TO P11,

P20 TO P21, P22 TO P29,

P31 TO P32, P33 TO P40

t20

t9 t10

t19

Figure 6. Digital Input Port and Control Input Timing

Rev. B | Page 7 of 20

ADV7403

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