ATWINC1500B-MU 查看數據表（PDF） - Atmel Corporation

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ATWINC1500B-MU

IEEE 802.11 b/g/n Network Controller SoC

Atmel Corporation 

Figure 8-1. I2C Slave Timing Diagram

tSUDAT

tPR

tHDDAT

tSUSTO

tBUF

SDA

tHL

tLH

tWL

tLH

tHL

SCL

tHDSTA

tWH

tPR

fSCL

tPR

tSUSTA

Table 8-2. I2C Slave Timing Parameters

Parameter

SCL Clock Frequency

SCL Low Pulse Width

SCL High Pulse Width

SCL, SDA Fall Time

Symbol

fSCL

tWL

tWH

tHL

Min.

0

1.3

0.6

SCL, SDA Rise Time

tLH

START Setup Time

tSUSTA

0.6

START Hold Time

tHDSTA

0.6

SDA Setup Time

tSUDAT

100

0

SDA Hold Time

tHDDAT

40

STOP Setup time

tSUSTO

0.6

Bus Free Time Between

STOP and START

tBUF

1.3

Glitch Pulse Reject

tPR

0

Max.

400

300

300

50

Units

kHz

µs

ns

µs

ns

µs

ns

Remarks

This is dictated by external

components

Slave and Master Default

Master Programming Op-

tion

18

A1tmel ATWINC1500B-MU [DATASHEET]

Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016

8

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