M24C01-W 查看數據表（PDF） - STMicroelectronics

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M24C01-W

16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit serial I²C bus EEPROM

STMicroelectronics 

M24C16, M24C08, M24C04, M24C02, M24C01

Signal description

2.4

2.4.1

2.4.2

2.4.3

2.4.4

Supply voltage (VCC)

Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Table 6, Table 7 and

Table 8). In order to secure a stable DC supply voltage, it is recommended to decouple the

VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the

VCC/VSS package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal write cycle (tW).

Power-up conditions

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage

defined in Table 6, Table 7 and Table 8 and the rise time must not vary faster than 1 V/µs.

Device reset

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)

circuit is included. At power-up (continuous rise of VCC), the device does not respond to any

instruction until VCC reaches the power-on-reset threshold voltage (this threshold is lower

than the minimum VCC operating voltage defined in Table 6, Table 7 and Table 8). When

VCC passes over the POR threshold, the device is reset and enters the Standby Power

mode. The device, however, must not be accessed until VCC reaches a valid and stable VCC

voltage within the specified [VCC(min), VCC(max)] range.

In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops

below the power-on-reset threshold voltage, the device stops responding to any instruction

sent to it.

Power-down conditions

During power-down (continuous decrease in VCC), the device must be in the Standby Power

mode (mode reached after decoding a Stop condition, assuming that there is no internal

write cycle in progress).

Figure 5. Maximum RP value versus bus parasitic capacitance (C) for an I²C bus

100

10

4 kΩ

Rbus

Here Rbus × Cbus = 120 ns

× Cbus

= 400 ns

1

10

30 pF

100

Bus line capacitor (pF)

When tLOW = 1.3 µs (min value for

fC = 400 kHz), the Rbus × Cbus

time constant must be below the

400 ns time constant line

represented on the left.

VCC

Rbus

1000

I²C bus

master

SCL

SDA

M24xxx

Cbus

ai14796b

Doc ID 5067 Rev 17

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