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PI6C3Q993AQ 查看數據表(PDF) - Pericom Semiconductor

零件编号
产品描述 (功能)
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PI6C3Q993AQ Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
PI6C3Q991A, PI6C3Q993A
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
3.3V Programmable Skew PLL Clock Driver
SuperClock
Features
• PI6C3Q99X family provides following products:
PI6C3Q991A: 32-pin PLCC version
PI6C3Q993A: 28-pin QSOP version
• Inputs are 5V Tolerant
• 4 pairs of programmable skew outputs
• Low skew: 200ps same pair; 250ps all outputs
• Selectable positive or negative edge synchronization:
Excellent for DSP applications
• Synchronous output enable
• Input frequency: 3.75 MHz to 85 MHz
• Output frequency: 15 MHz to 85MHz
• 2x, 4x, 1/2, and 1/4 outputs
• 3 skew grades:
PI6C3Q99x: tSKEW0 <750ps
PI6C3Q99x-5: tSKEW0 <500ps
PI6C3Q99x-2: tSKEW0 <250ps
• 3-level inputs for skew and PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter: < 200ps peak-to-peak
• Industrial temperature range
• Pin-to-pin compatible with IDT QS5V991A and QS5V993A
• Available in 32-pin PLCC and 28-pin QSOP
Description
The PI6C3Q99X family, a high-fanout 3.3V PLL-based clock driver,
is intended for high-performance computing and data-communica-
tion applications. A key feature of the programmable skew is the
ability of outputs to lead or lag the REF input signal. The PI6C3Q991A
has 8 programmable skew outputs in 4 banks of 2, while the
PI6C3Q993A has 6 programmable skew outputs and 2 zero skew
outputs. Skew is controlled by 3-level input signals that may be
hard-wired to appropriate HIGH-MID-LOW levels.
When the GND/sOE pin is held LOW, all the outputs are synchro-
nously enabled. However, if GND/sOE is held HIGH, all outputs
except 3Q0 and 3Q1 are synchronously disabled. Furthermore,
when the V CCQ /PE is held HIGH, all outputs are synchronized with
the positive edge of the REF clock input. When VCCQ /PE is held
LOW, all outputs are synchronized with the negative edge of REF.
Both devices have LVTTL outputs with 12mA balanced drive
outputs.
Pin Configurations
PI6C3Q991A
PI6C3Q993A
3F1
4F0
4F1
VCCQ/PE
VCCN
4Q1
4Q0
GND
GND
4 3 2 1 32 31 30
5
29
6
28
7
27
8
32-Pin
26
9
J
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
2F0
GND/sOE
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
REF
VCCQ
FS
3F0
3F1
VCCQ/PE
VCCN
4Q1
4Q0
GND
3Q1
3Q0
VCCN
FB
1
28
2
27
3
26
4
25
5
24
6 28-Pin 23
7
Q
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
GND
TEST
2F1
2F0
GND/sOE
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
2Q0
2Q1
1
PS8628 08/15/02

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