DSC400-4334Q0022 查看數據表（PDF） - Microchip Technology
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DSC400-4334Q0022 Datasheet PDF : 11 Pages
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Microchip Technology Inc.
DSC400-4334Q0022
Operational Description
The DSC400-4334Q0022 is a crystal-less™ clock generator. Unlike older clock generators in the industry, it does not require an
external crystal to operate; it relies on integrated MEMS resonators that interface with internal PLLs. This technology enhances
performance and reliability by allowing tighter frequency stability over a far wider temperature range. In addition, the higher
resistance to shock and vibration decreases the aging rate, greatly improving product life in the system.
Inputs
There are 4 input signals in the device. Each has an internal (40kOhms) pull up, which defaults the selection to a high (1). Inputs
can be controlled through hardware strapping method with a resistor to ground to assert the input low (0). Inputs may also be
controlled by other components' GPIOs. In case more than one frequency set is desired, FSB1 and FSB2 are used for independent-
ly selecting one of two sets frequency per bank. FSB1 selects the pre-configured frequency set on Bank 1 (CLK1 and CLK4) and
FSB2 selects the pre-configured frequency set on Bank 2 (CLK3 and CLK2). If there is a requirement to disable outputs, the
inputs OE1 and OE2 are used to disable the banks of outputs. Outputs are disabled in tristate (Hi-Z) mode, see Table 1 below.
OE1
OE2
0
0
0
1
1
0
1
1
Outputs
Bank 1 (CLK1 and CLK4)
Hi-Z
Hi-Z
Running
Running
Table 1. Output Enable (OE) Selection Table
Bank 2 (CLK3 and CLK2)
Hi-Z
Running
Hi-Z
Running
The four outputs are grouped into two banks. Each bank is supplied by an independent VDD to allow for optimized noise
isolation between the two banks. Each bank provides two synchronous outputs generated by a common PLL:
• Bank 1 is composed of outputs CLK1 and CLK4
• Bank 2 is composed of outputs CLK3 and CLK2
Each output maybe pre-configured independently to be one of the following formats: LVCMOS, LVDS, LVPECL or HCSL.
In case the output is configured to be single ended (LVCMOS only), the frequency is generated on the true output (CLKx+) and
the complement output (CLKx-) is shut off in a low state. Frequencies can be chosen from 2.3MHz to 460MHz for differential
outputs and from 2.3MHz to 170MHz on LVCMOS outputs.
Output Clock Frequencies
Output
Frequency (MHz)
CLK1
125
CLK2
100
CLK3
100
CLK4
125
Power
VDD1 and VDD2 supply the power to banks 1 and 2 respectively. Each VDD may have different supply voltage from the other
as long as it is within the 2.25V to 3.6V range. Each VDD pin should have a 0.1µF capacitor to filter high frequency noise.
VSS is common to the entire device. The exposed die paddle should be connected to VSS.
February 13, 2017
4852
4
Revision 1.0
tcghelp@microchip.com
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