DSA63XX
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, VDD = 1.8V –5% to 3.3V +10%, TA = –40°C to +125°C.
Parameters
Sym.
Min. Typ.
Max.
Units
Conditions
Output Logic Levels
VOH
0.8 x VDD —
—
VOL
—
—
0.2 x VDD
Output Logic High, I = 3 mA,
Std. Drive
V
Output Logic High, I = 6 mA,
High Drive
Output Logic Low, I = –3 mA,
Std. Drive
V
Output Logic Low, I = –6 mA,
High Drive
—
1
1.5
tRX/tFX
Output Transition Time
—
0.5
1.0
Rise Time/Fall Time
—
1.2
2.0
tRY/tFY
—
0.6
1.2
ns DSA61x2 VDD = 1.8V
High Drive,
20% to 80%
ns CL = 15 pF VDD = 2.5V/3.3V
ns DSA61x1 VDD = 1.8V
Std Drive,
20% to 80%
ns CL = 10 pF VDD = 2.5V/3.3V
Period Jitter, RMS
JPER
—
8.5
—
7
—
fOUT =
VDD = 1.8V
—
psRMS 27 MHz,
Spread Off
VDD = 2.5V/3.3V
Cycle-to-Cycle Jitter
(Peak)
Period Jitter
(Peak-to-Peak)
—
50
70
fOUT =
VDD = 1.8V
JCy–Cy
—
35
60
ps 27 MHz,
Spread Off VDD = 2.5V/3.3V
—
70
—
fOUT =
VDD = 1.8V
JPP
—
60
—
ps 27 MHz,
Spread Off VDD = 2.5V/3.3V
Spread Spectrum
Modulation Frequency
fSS
—
33
—
kHz —
Note 1:
2:
3:
4:
5:
6:
7:
8:
Pin 4 VDD should be filtered with 0.1 μF capacitor.
Not including current through pull-up resistor on EN pin (if configured).
Includes frequency variations due to initial tolerance, temp. and power supply voltage.
Input waveform must be monotonic with rise/fall time < 10 ms
Output Disable time takes up to two periods of the output waveform + 200 ns.
For parts configured with OE, not Standby.
Output is enabled if pad is floated or not connected.
Time to reach 90% of target VDD. Power ramp rise must be monotonic.
DS20006189A-page 4
2019 Microchip Technology Inc.