74HC163-Q100 查看數據表（PDF） - Nexperia B.V. All rights reserved

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74HC163-Q100

Presettable synchronous 4-bit binary counter; synchronous reset

Nexperia B.V. All rights reserved 

Nexperia

74HC163-Q100; 74HCT163-Q100

Presettable synchronous 4-bit binary counter; synchronous reset

6. Functional description

Table 3. Function table[1]

Operating mode

Reset (clear)

Parallel load

Count

Hold (do nothing)

Inputs

Outputs

MR

CP

CEP CET PE

Dn

Qn

TC

I

↑

X

X

X

X

L

L

h

↑

X

X

I

I

L

L

h

↑

X

X

I

h

H

L

h

↑

h

h

h

X

count

h

X

I

X

h

X

qn

L

h

X

X

I

h

X

qn

L

[1] The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH);

H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;

L = LOW voltage level;

I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;

q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition;

X = don’t care;

↑ = LOW-to-HIGH clock transition.

0

1

2

3

4

15

5

14

6

13

7

Fig. 7. State diagram

12

11

10

9

8

aaa-012187

74HC_HCT163_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 12 October 2018

© Nexperia B.V. 2018. All rights reserved

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