BR24A01AFJ-WM 查看數據表（PDF） - ROHM Semiconductor

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BR24A01AFJ-WM

105℃ Operation I2C BUS EEPROM (2-Wire)

ROHM Semiconductor 

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●WP valid timing (write cancel)

WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP

valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte

write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of

data(in page write cycle, the first byte data) is cancel invalid area.

WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise

of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,

write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Figure 48.)

After execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).

・Rise of D0 taken clock

SCL

SDA

D1 D0 ACK

Enlarged view

SCL

・Rise of SDA

SDA

D0

ACK

Enlarged view

SDA

S

T

A

R

T

Slave

address

A

C

K

L

Word

address

A

C

K

L

A

D7 D6 D5 D4 D3 D2 D1 D0 C

K

L

Data

AS

CT

KO

LP

tW R

WP cancels invalid area

WP

WP cancels valid area

Write forced end

Data is not written.

Data not guaranteed

Figure 48. WP valid timing

●Command cancel by start condition and stop condition

During command input, by continuously inputting start condition and stop condition, command can be cancelled.

(Refer to Figure 49.)

However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop

condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by

start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not

determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in

succession, carry out random read cycle.

SCL

SDA

1

0

1

0

Start condition Stop condition

Figure 49. Case of cancel by start, stop condition during slave address input

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