S-25A010A0A-J8T2UD 查看數據表（PDF） - Seiko Instruments Inc

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S-25A010A0A-J8T2UD

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM

Seiko Instruments Inc 

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM

S-25A010A/020A/040A

Rev.5.2_01

 Operation

1. Status register

The status register's organization is below. The status register can write and read by a specific instruction.

b7

b6

b5

b4

b3

b2

b1

b0

1

1

1

1

BP1

BP0

WEL

WIP

Block Protect

Write Enable Latch

Write In Progress

Figure 10 Organization of Status Register

The status / control bits of the status register are as follows.

1. 1 BP1, BP0 (b3, b2) : Block Protect

Bit BP1 and BP0 are composed of the nonvolatile memory. The area size of Software Protect with respect to

WRITE instructions is defined by the BP1 and BP0 bits. Rewriting these bits is possible by the WRSR instruction.

To protect the memory area against the WRITE instruction, set either or both of bit BP1 and BP0 to "1". Rewriting

bit BP1 and BP0 is possible unless they are in Hardware Protect mode. Refer to " Protect Operation" for details

of Block Protect.

1. 2 WEL (b1) : Write Enable Latch

Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL

is "1", this is the status that Write Enable Latch is set. If bit WEL is "0", Write Enable Latch is in reset, so that this

IC does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;

• The power supply voltage is dropping

• At power-on

• After performing WRDI

• After the completion of write operation by the WRSR instruction

• After the completion of write operation by the WRITE instruction

• After setting WP pin to "L"

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