Data Sheet
Figure 9.3 Read Identification (RDID) Command Sequence and Data-Out Sequence
CS#
Mode 3
SCK
Mode 0
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31
Command
Hi-Z
SO
Manufacturer Identification
MSB
Device Identification
15 14 13
32 1 0
Table 9.1 Read Identification (RDID) Data-Out Sequence
Manufacturer Identification
01h
Device Identification
Memory Type
Memory Capacity
02h
14h
9.4 Write Enable (WREN)
The Write Enable (WREN) command (see Figure 9.4) sets the Write Enable Latch (WEL) bit to a 1, which
enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set
prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) command.
The host system must first drive CS# low, write the WREN command, and then drive CS# high.
Figure 9.4 Write Enable (WREN) Command Sequence
CS#
SCK
Mode 3
Mode 0
SI
01 23 4 567
Command
Hi-Z
SO
18
S25FL016A
S25FL016A_00_C3 January 7, 2008