HMP8156(1997) View Datasheet(PDF) - Intersil
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Description
Manufacturer
HMP8156 Datasheet PDF : 33 Pages
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HMP8156
TABLE 5. PIXEL INPUT AND CONTROL SIGNAL I/O TIMING
INPUT PORT SAMPLING
VIDEO TIMING CONTROL (NOTE)
CLK FREQUENCY
INPUT FORMAT
PIXEL DATA OVERLAY DATA INPUT SAMPLE OUTPUT ON
INPUT
OUTPUT
8-Bit YCbCr
Off Every rising edge Same edge that Every rising edge Any rising edge of Ignored
of CLK2
latches Y
of CLK2
CLK2
One-half
CLK2
On Rising edge of Same edge that Rising edge of Rising edge of
CLK2 when CLK latches Y data CLK2 when CLK CLK2 when CLK
is low.
is low.
is high.
One-half CLK2
16-Bit YCbCr,
16-Bit RGB,
or
24-Bit RGB
Off Rising edge of CLK2 when CLK is low
On 2nd rising edge of CLK2 when CLK is low
Rising edge of
CLK2 when CLK
is high.
Either rising
CLK2 edge when
CLK is high
One-half CLK2
One-fourth CLK2
BT.656
Off Every rising edge Same edge that Not Allowed
of CLK2
latches Y
Any rising edge of Ignored
CLK2
One-half
CLK2
On
Not Available
NOTE: Video timing control signals include HSYNC, VSYNC, BLANK and FIELD. The sync and blanking I/O directions are independent;
FIELD is always an output.
8-Bit YCbCr Format without 2X Upscaling
When 8-bit YCbCr format is selected and 2X upscaling is not
enabled, the data is latched on each rising edge of CLK2.
The pixel data must be [Cb Y Cr Y’ Cb Y Cr Y’. . . ], with the
first active data each scan line being Cb data. Overlay data
is latched when the Y input data is latched. The pixel and
overlay input timing is shown in Figure 1.
As inputs, BLANK, HSYNC, and VSYNC are latched on
each rising edge of CLK2. As outputs, BLANK, HSYNC, and
VSYNC are output following the rising edge of CLK2. If the
CLK pin is configured as an input, it is ignored. If configured
as an output, it is one-half the CLK2 frequency
8-Bit YCbCr Format with 2X Upscaling
When 8-bit YCbCr format is selected, the data is latched on
the rising edge of CLK2 while CLK is low. The pixel data
must be [Cb Y Cr Y’ Cb Y Cr Y’. . . ], with the first active data
each scan line being Cb data. Overlay data is latched on the
rising edge of CLK2 that latches Y pixel input data. The pixel
and overlay input timing is shown in Figure 2.
As inputs, BLANK, HSYNC, and VSYNC are latched on the
rising edge of CLK2 while CLK is low. As outputs, HSYNC,
VSYNC, and BLANK are output following the rising edge of
CLK2 while CLK is high. In this mode of operation, CLK is
one-half the CLK2 frequency.
CLK2
P8-P15
OL0-OL2,
M1, M0
BLANK
(INPUT)
BLANK
(OUTPUT)
Cb 0
Y0
Cr 0
Y1
Cb 2
Y2
PIXEL 0
PIXEL 1
PIXEL 2
YN
PIXEL N
FIGURE 1. PIXEL AND OVERLAY INPUT TIMING - 8-BIT YCBCR WITHOUT 2X UPSCALING
6
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