HMP8156(1997) View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

HMP8156
(Rev.:1997)

NTSC/PAL Encoder

Intersil 

HMP8156

CLK2

CLK

P8-P15

Cb 0

Y0

Cr 0

Y1

Cb 2

Y2

YN

OL0-OL2,

M1, M0

BLANK

(INPUT)

BLANK

(OUTPUT)

PIXEL 0

PIXEL 1

PIXEL 2

PIXEL N

FIGURE 2. PIXEL AND OVERLAY INPUT TIMING - 8-BIT YCBCR WITH 2X UPSCALING

16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats without

2X Upscaling

When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format

is selected without 2X upscaling, the pixel data is latched on

the rising edge of CLK2 while CLK is low. Overlay data is

also latched on the rising edge of CLK2 while CLK is low.

The pixel and overlay input timing is shown in Figures 3 - 5.

As inputs, BLANK, HSYNC, and VSYNC are latched on the

rising edge of CLK2 while CLK is low. As outputs, HSYNC,

VSYNC, and BLANK are output following the rising edge of

CLK2 while CLK is high. In these modes of operation, CLK is

one-half the CLK2 frequency.

16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats with 2X

Upscaling

When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format

is selected and 2X upscaling is enabled, data is latched on

the rising edge of CLK2 while CLK is low. Overlay data is

latched on the rising edge of CLK2 while CLK is low. The

pixel and overlay input timing is shown in Figures 6-8

As inputs, BLANK, HSYNC, and VSYNC are latched on the

rising edge of CLK2 while CLK is low. As outputs, HSYNC,

VSYNC, and BLANK are output following the rising edge of

CLK2 while CLK is high. CLK is one-fourth the CLK2 fre-

quency.

CLK2

CLK

P8-P15

P0-P7

OL0-OL2,

M1, M0

BLANK

(INPUT)

BLANK

(OUTPUT)

Y0

Y1

Y2

Y3

Y4

Y5

Cb 0

Cr 0

Cb 2

Cr 2

Cb 4

Cr 4

PIXEL 0 PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4 PIXEL 5

YN

Cr N-1

PIXEL N

FIGURE 3. PIXEL AND OVERLAY INPUT TIMING 6-BIT YCBCR WITHOUT 2X UPSCALING

7

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