A75 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

A75

PENTIUM® PROCESSOR

Intel 

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

E

Symbol

PHIT#

PHITM#

PICCLK

PICD0-1

[DPEN#]

[APICEN]

PM/BP[1:0]

PRDY

PWT

R/S#

RESET

SCYC

SMI#

Type*

I/O

I/O

I

I/O

O

O

O

I

I

O

I

Table 2. Quick Pin Reference (Continued)

Name and Function

Private hit is a hit indication used when two Pentium processor 75/90/100/120/

133/150/166/200 are configured in dual processing mode, in order to maintain

local cache coherency. PHIT# should be left unconnected if only one Pentium

processor 75/90/100/120/133/150/166/200 exists in a system.

Private modified hit is a hit indication used when two Pentium processor

75/90/100/120/133/150/166/200 are configured in dual processing mode, in order

to maintain local cache coherency. PHITM# should be left unconnected if only one

Pentium processor 75/90/100/120/133/150/166/200 exists in a system.

The APIC interrupt controller serial data bus clock is driven into the

programmable interrupt controller clock input of the Pentium processor

75/90/100/120/133/150/166/200.

Programmable interrupt controller data lines 0-1 of the Pentium processor

75/90/100/120/133/150/166/200 comprise the data portion of the APIC 3-wire bus.

They are open-drain outputs that require external pull-up resistors. These signals

share pins with DPEN# and APICEN respectively.

These pins function as part of the performance monitoring feature.

The breakpoint 1-0 pins are multiplexed with the performance monitoring 1-0

pins. The PB1 and PB0 bits in the Debug Mode Control Register determine if the

pins are configured as breakpoint or performance monitoring pins. The pins come

out of RESET configured for performance monitoring.

The probe ready output pin indicates that the processor has stopped normal

execution in response to the R/S# pin going active, or Probe Mode being entered.

The page write through pin reflects the state of the PWT bit in CR3, the page

directory entry, or the page table entry. The PWT pin is used to provide an

external write back indication on a page-by-page basis.

The run/stop input is an asynchronous, edge-sensitive interrupt used to stop the

normal execution of the processor and place it into an idle state. A high to low

transition on the R/S# pin will interrupt the processor and cause it to stop

execution at the next instruction boundary.

RESET forces the Pentium processor 75/90/100/120/133/150/166/200 to begin

execution at a known state. All the Pentium processor 75/90/100/120/133/150/

166/200 internal caches will be invalidated upon the RESET. Modified lines in the

data cache are not written back. FLUSH#, FRCMC# and INIT are sampled when

RESET transitions from high to low to determine if tristate test mode or checker

mode will be entered, or if BIST will be run.

The split cycle output is asserted during misaligned LOCKed transfers to indicate

that more than two cycles will be locked together. This signal is defined for locked

cycles only. It is undefined for cycles which are not locked.

The system management interrupt causes a system management interrupt

request to be latched internally. When the latched SMI# is recognized on an

instruction boundary, the processor enters System Management Mode.

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