FV75 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FV75

PENTIUM® PROCESSOR

Intel 

E

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

Symbol

CACHE#

CLK

CPUTYP

D/C#

D/P#

D63-D0

DP7-DP0

Type*

O

I

I

O

O

I/O

I/O

Table 2. Quick Pin Reference (Continued)

Name and Function

For Pentium processor 75/90/100/120/133/150/166/200 -initiated cycles the cache

pin indicates internal cacheability of the cycle (if a read), and indicates a burst

write back cycle (if a write). If this pin is driven inactive during a read cycle, the

Pentium processor 75/90/100/120/133/150/166/200 will not cache the returned

data, regardless of the state of the KEN# pin. This pin is also used to determine

the cycle length (number of transfers in the cycle).

The clock input provides the fundamental timing for the Pentium processor

75/90/100/120/133/150/166/200. Its frequency is the operating frequency of the

Pentium processor 75/90/100/120/133/150/166/200 external bus, and requires

TTL levels. All external timing parameters except TDI, TDO, TMS, TRST#, and

PICD0-1 are specified with respect to the rising edge of CLK.

NOTE:

It is recommended that CLK begin toggling within 150 ms after VCC reaches its

proper operating level. This recommendation is to ensure long-term reliability of

the device.

CPU type distinguishes the Primary processor from the Dual processor. In a

single processor environment, or when the Pentium processor 75/90/100/120/133/

150/166/200 is acting as the Primary processor in a dual processing system,

CPUTYP should be strapped to VSS. The Dual processor should have CPUTYP

strapped to VCC. For the Pentium OverDrive processor, CPUTYP will be used to

determine whether the bootup handshake protocol will be used (in a dual socket

system) or not (in a single socket system).

The data/code output is one of the primary bus cycle definition pins. It is driven

valid in the same clock as the ADS# signal is asserted. D/C# distinguishes

between data and code or special cycles.

The dual/primary processor indication. The Primary processor drives this pin low

when it is driving the bus, otherwise it drives this pin high. D/P# is always driven.

D/P# can be sampled for the current cycle with ADS# (like a status pin). This pin

is defined only on the Primary processor. Dual processing is supported in a

system only if both processors are operating at identical core and bus

frequencies. Within these restrictions, two processors of different steppings may

operate together in a system.

These are the 64 data lines for the processor. Lines D7-D0 define the least

significant byte of the data bus; lines D63-D56 define the most significant byte of

the data bus. When the CPU is driving the data lines, they are driven during the

T2, T12, or T2P clocks for that cycle. During reads, the CPU samples the data

bus when BRDY# is returned.

These are the data parity pins for the processor. There is one for each byte of the

data bus. They are driven by the Pentium processor 75/90/100/120/133/150/166/

200 with even parity information on writes in the same clock as write data. Even

parity information must be driven back to the Pentium processor 75/90/100/120/

133/150/166/200 on these pins in the same clock as the data to ensure that the

correct parity check status is indicated by the Pentium processor 75/90/100/120/

133/150/166/200. DP7 applies to D63-56, DP0 applies to D7-0.

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