FV75 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FV75

PENTIUM® PROCESSOR

Intel 

E

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

Symbol

FRCMC#

HIT#

HITM#

HLDA

HOLD

IERR#

Type*

I

O

O

O

I

O

Table 2. Quick Pin Reference (Continued)

Name and Function

The functional redundancy checking master/checker mode input is used to

determine whether the Pentium processor 75/90/100/120/133/150/166/200 is

configured in master mode or checker mode. When configured as a master, the

Pentium processor 75/90/100/120/133/150/166/200 drives its output pins as

required by the bus protocol. When configured as a checker, the Pentium

processor 75/90/100/120/133/150/166/200 tristates all outputs (except IERR# and

TDO) and samples the output pins.

The configuration as a master/checker is set after RESET and may not be

changed other than by a subsequent RESET.

The hit indication is driven to reflect the outcome of an inquire cycle. If an inquire

cycle hits a valid line in either the Pentium processor 75/90/100/120/133/150/166/

200 data or instruction cache, this pin is asserted two clocks after EADS# is

sampled asserted. If the inquire cycle misses the Pentium processor 75/90/100/

120/133/150/166/200 cache, this pin is negated two clocks after EADS#. This pin

changes its value only as a result of an inquire cycle and retains its value between

the cycles.

The hit to a modified line output is driven to reflect the outcome of an inquire

cycle. It is asserted after inquire cycles which resulted in a hit to a modified line in

the data cache. It is used to inhibit another bus master from accessing the data

until the line is completely written back.

The bus hold acknowledge pin goes active in response to a hold request driven

to the processor on the HOLD pin. It indicates that the Pentium processor 75/90/

100/120/133/150/166/200 has floated most of the output pins and relinquished the

bus to another local bus master. When leaving bus hold, HLDA will be driven

inactive and the Pentium processor 75/90/100/120/133/150/166/200 will resume

driving the bus. If the Pentium processor 75/90/100/120/133/150/166/200 has a

bus cycle pending, it will be driven in the same clock that HLDA is de-asserted.

In response to the bus hold request, the Pentium processor 75/90/100/120/133/

150/166/200 will float most of its output and input/output pins and assert HLDA

after completing all outstanding bus cycles. The Pentium processor 75/90/100/

120/133/150/166/200 will maintain its bus in this state until HOLD is de-asserted.

HOLD is not recognized during LOCK cycles. The Pentium processor 75/90/100/

120/133/150/166/200 will recognize HOLD during reset.

The internal error pin is used to indicate two types of errors, internal parity errors

and functional redundancy errors. If a parity error occurs on a read from an

internal array, the Pentium processor 75/90/100/120/133/150/166/200 will assert

the IERR# pin for one clock and then shutdown. If the Pentium processor

75/90/100/120/133/150/166/200 is configured as a checker and a mismatch

occurs between the value sampled on the pins and the corresponding value

computed internally, the Pentium processor 75/90/100/120/133/150/166/200 will

assert IERR# two clocks after the mismatched value is returned.

17

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