V54C3128164VALS6 View Datasheet(PDF) - Mosel Vitelic Corporation

Part Name

Description

Manufacturer

V54C3128164VALS6

128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4

Mosel Vitelic Corporation  

MOSEL VITELIC

V54C3128(16/80/40)4V(T/S)

AC Characteristics 1,2, 3

TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns

Limit Values

-6

-7PC

-7

-8PC

# Symbol Parameter

Min. Max. Min. Max. Min. Max. Min. Max. Unit Note

Clock and Clock Enable

1

tCK

Clock Cycle Time

CAS Latency = 3

CAS Latency = 2

s

6–7–7–

8

–

ns

7.5 – 7.5 – 10 – 10 –

ns

2

tCK

Clock Frequency

CAS Latency = 3

CAS Latency = 2

– 166 – 143 – 143 – 125 MHz

– 133 – 133 – 100 – 100 MHz

3

tAC

Access Time from Clock

CAS Latency = 3

CAS Latency = 2

2, 4

– 5.4 – 5.4 – 5.4 –

6

ns

_ 5.4 _ 5.4 _ 6

_

6

ns

4

tCH

Clock High Pulse Width

5

tCL

Clock Low Pulse Width

6

tT

Transition Tim

Setup and Hold Times

2.5 – 2.5 – 2.5 –

3

–

ns

2.5 – 2.5 – 2.5 –

3

–

ns

0.3 1.2 0.3 1.2 0.3 1.2 0.5 10 ns

7

tIS

Input Setup Time

8

tIH

Input Hold Time

9

tCKS Input Setup Time

10

tCKH CKE Hold Time

11

tRSC Mode Register Set-up Time

12

tSB

Power Down Mode Entry Time

Common Parameters

1.5 – 1.5 – 1.5 –

2

–

ns

5

0.8 – 0.8 – 0.8 –

1

–

ns

5

1.5 – 1.5 – 1.5 –

2

–

ns

5

0.8 – 0.8 – 0.8 –

1

–

ns

5

12 – 14 – 14 – 16 –

ns

060707

0

8

ns

13

tRCD Row to Column Delay Time

12 – 15 – 15 – 20 –

ns

6

14

tRP

Row Precharge Time

15 – 15 – 15 – 20 –

ns

6

15

tRAS Row Active Time

40 100K 42 100K 42 100K 45 100k ns

6

16

tRC

Row Cycle Time

60 – 60 – 60 – 60 –

ns

6

17

tRRD Activate(a) to Activate(b) Command Period 12 – 14 – 14 – 16 –

ns

6

18

tCCD CAS(a) to CAS(b) Command Period

1–

1–

1

–

1

– CLK

Refresh Cycle

19

tREF Refresh Period (4096 cycles)

20 tSREX Self Refresh Exit Time

— 64 — 64 — 64 — 64 ms

1

—

1

—

1

—

1

— CLK

V54C3128(16/80/40)4V(T/S) Rev.1.5 March 2003

16

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