V54C3128164VALS6 View Datasheet(PDF) - Mosel Vitelic Corporation

Part Name

Description

Manufacturer

V54C3128164VALS6

128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4

Mosel Vitelic Corporation  

MOSEL VITELIC

V54C3128(16/80/40)4V(T/S)

1. Bank Activate Command Cycle

(CAS latency = 3)

T0

T1

T

CLK

ADDRESS

Bank A

Row Addr.

COMMAND

: “H” or “L”

Bank A

Activate

tRCD

NOP

NOP

T

T

T

..........

Bank A

..........

Bank B

Col. Addr.

Row Addr.

tRRD

Write A

with Auto

Precharge

..........

Bank B

Activate

NOP

tRC

T

Bank A

Row Addr.

Bank A

Activate

2. Burst Read Operation

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND READ A

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CAS latency = 2

tCK2, I/O’s

CAS latency = 3

tCK3, I/O’s

DOUT A0

DOUT A1

DOUT A2

DOUT A3

DOUT A0

DOUT A1

DOUT A2

DOUT A3

NOP

V54C3128(16/80/40)4V(T/S) Rev.1.5 March 2003

20

Share Link: