AD1853 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD1853 Datasheet PDF : 16 Pages
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AD1853
POWER
Min
Typ
Max
Units
Supplies
Voltage, Analog and Digital
4.5
5
5.5
V
Analog Current
12
15
mA
Digital Current
28
33
mA
Dissipation
Operation—Both Supplies
200
mW
Operation—Analog Supply
60
mW
Operation—Digital Supply
140
mW
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
–77
dB
20 kHz 300 mV p-p Signal at Analog Supply Pins
Specifications subject to change without notice.
–72
dB
TEMPERATURE RANGE
E Specifications Guaranteed
Functionality Guaranteed
Storage
T Specifications subject to change without notice.
Min
Typ
25
0
–55
Max
70
125
Units
°C
°C
°C
DIGITAL FILTER CHARACTERISTICS
E Sample Rate (kHz) Passband (kHz)
44.1
DC–20
48
DC–21.8
L 96
DC–39.95
192
DC–87.2
Stopband (kHz)
24.1–328.7
26.23–358.28
56.9–327.65
117–327.65
Stopband Attenuation (dB)
110
110
115
95
O Specifications subject to change without notice.
Passband Ripple (dB)
± 0.0002
± 0.0002
± 0.0005
+0/–0.04 (DC–21.8 kHz)
+0/–0.5 (DC–65.4 kHz)
+0/–1.5 (DC–87.2 kHz)
GROUP DELAY
Chip Mode
Group Delay Calculation
S INT8x Mode
INT4x Mode
INT2x Mode
5553/(128 × FS)
5601/(64 × FS)
5659/(32 × FS)
B Specifications subject to change without notice.
FS
48 kHz
96 kHz
192 kHz
Group Delay
903.8
911.6
921
Units
µs
µs
µs
DIGITAL TIMING (Guaranteed Over 0؇C to +70؇C, AVDD = DVDD = +5.0 V ؎ 10%)
O Min
Units
tDMP
MCLK Period (With FMCLK = 256 × FLRCLK)*
54
ns
tDML
MCLK LO Pulsewidth (All Modes)
0.4 × tDMP
ns
tDMH
MCLK HI Pulsewidth (All Modes)
0.4 × tDMP
ns
tDBH
BCLK HI Pulsewidth
20
ns
tDBL
BCLK LO Pulsewidth
20
ns
tDBP
BCLK Period
140
ns
tDLS
LRCLK Setup
20
ns
tDLH
LRCLK Hold (DSP Serial Port Mode Only)
5
ns
tDDS
SDATA Setup
5
ns
t
SDATA Hold
DDH
10
ns
t
PDRP
PD/RST LO Pulsewidth
5
ns
*Higher MCLK frequencies are allowable when using the on-chip Master Clock Auto-Divide feature.
Specifications subject to change without notice.
REV. A
–3–
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