GS841E18AT/B-166/150/130/100
Pipelined DCD Read-Write Cycle Timing
CK
ADSP
Single Read
Single Write
tKL
Burst Read
tS tH
tKH
tKC
ADSP is blocked by E1 inactive
tS tH ADSC initiated read
ADSC
tS tH
ADV
A0–An
tS tH
RD1
WR1
RD2
GW
tS tH
tS
tH
BW
BA–BD
E1
tS tH
tH
tS
WR1
E1 masks ADSP
tS tH
E2*
E2 only sampled with ADSP and ADSC
G
Hi-Z
DQA–DQD
tOE tOHZ
tKQ
Q1A
tS tH
D1a
Q2A
Q2B
Q2c Q2D
Rev: 1.00 10/2001
18/29
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.