MTL005 View Datasheet(PDF) - Myson Century Inc
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Manufacturer
MTL005 Datasheet PDF : 50 Pages
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MYSON
TECHNOLOGY
MTL005
Rev 0.9
¨ Random Read
The operation of Random Read allows accessing any address. Before reading data operation, it must issue a
“dummy write” operation— a start condition, a slave address with R/W bit set to 0, and word address for read.
After responding an Acknowledge, MTL005 then transmits eight bits data right after the master generating
the start condition and slave address with R/W bit set to 1. After completion of receiving data, the master will
generate a stop condition instead of an Acknowledge. Ref. Fig 3.5.5.
S
T
A
R
SLAVE
T ADDRESS
WORD
ADDRESS
S
T
A
R
SLAVE
T
ADDRESS
S
T
DATA
O
P
SDA
WA
A
RA
C
C
C
K
K
K
Fig. 3.4.5 Random Read
¨ Sequential Read
The initial step can be as either Current Address Read or Random Read. The first read data is transmitted
the same manner as other read methods. However, the master generates an Acknowledge indicating that it
requires more data to read. MTL005 continues to output data for each Acknowledge received. The output
data is sequential and the internal address counter increments by one for next read data. Ref. Fig. 3.5.6.
S
T
A
R
T
SDA
SLAVE
ADDRESS
RA
C
K
DATA n
DATA n+1
A
A
C
C
K
K
S
T
DATA n+x
O
P
Fig. 3.4.6 Sequential Read
3.4.2 Interrupt
MTL005 supports one interrupt output signal (IRQ) which can be programmed to provide SYNC related or
function status related interrupts to the system. Upon receiving the interrupt request, Firmware needs to first
check the interrupt event by reading the Interrupt Flag Control registers (Reg. E8h and E9h) to decide what
events are happening. After the operation is finished, Firmware needs to clear interrupt status by writing the
same registers Reg. E8h and E9h. Furthermore, by using the Interrupt Flag Enable registers (Reg. EAh and
EBh), each interrupt event can be masked.
3.4.3 Update Register Contents
I/O write operation to some consecutive register set can have the “Double Buffer” effect by setting the
Reg. C1h/D4. Written data is first stored in an intermediate bank of latches and then transferred to the active
register set by setting Reg. C1h/D1-0.
Revision 0.9
- 14 -
2000/12/29
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