MTL005 View Datasheet(PDF) - Myson Century Inc

Part Name

Description

Manufacturer

MTL005

XGA Flat Panel Controller

Myson Century Inc 

MYSON

TECHNOLOGY

MTL005

Rev 0.9

3.5 On-Chip PLL

General Description

The MTL005 needs two clock sources to drive synchronous circuits on chip. These clocks are generated

from the internal Phase Lock Loop (PLL) circuits with reference to the oscillator clock which is applied to pin

XI and XO by an external quartz crystal at 14.31818 MHz. First one is the same as to the oscillator clock at

frequency (14.31818 MHz) to detect and measure graphic vertical and horizontal SYNC Frequency, Polarity

as well as Presence. The second is the display clock for display controller on chip and output signals to LCD

panel.

3.5.1 Reference Clock

It is the counting basis of counter values in SYNC Processor such as VS and HS period count registers; that

is, the read back values from these registers must multiply the period of this clock to estimate VS and HS

frequency. Incorporating with polarity and frequency information of VS and HS, it can show the input graphic

image mode and pixel clock frequency.

3.5.2 Display Clock

This clock is the synchronous clock for LCD panel. According to the LCD panel resolution of applications, the

display clock range is from 50 MHz to 200 MHz by means of choosing a set of appropriate values for M, N as

well as R. The formula to calculate desired frequency of display clock is as follows:

fmclk = fosc5(M+2)/(N+2)51/R

Where fmclk

fosc

M

N

R

: the desired display clock

: oscillator clock with 14.31818 MHz

: post-divider ratio

: pre-divider ratio

: optional divider ratio

Revision 0.9

- 15 -

2000/12/29

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