IT8502G View Datasheet(PDF) - ITE Tech. INC.
Part Name
Description
Manufacturer
IT8502G Datasheet PDF : 398 Pages
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IT8502E/F/G
7.20.3.1 ROM Address Match Interrupt............................................................................ 332
7.20.3.2 EC Memory Snoop (ECMS) ............................................................................... 332
7.20.4 EC Interface Registers ................................................................................................... 333
7.20.4.1 Trigger 1 Address Low Byte Register (BKA1L) ................................................... 333
7.20.4.2 Trigger 1 Address Middle Byte Register (BKA1M) .............................................. 333
7.20.4.3 Trigger 1 Address High Byte Register (BKA1H) ................................................. 333
7.20.4.4 Trigger 2 Address Low Byte Register (BKA2L) ................................................... 333
7.20.4.5 Trigger 2 Address Middle Byte Register (BKA2M) .............................................. 333
7.20.4.6 Trigger 2 Address High Byte Register (BKA2H) ................................................. 334
7.20.4.7 Trigger 3 Address Low Byte Register (BKA3L) ................................................... 334
7.20.4.8 Trigger 3 Address Middle Byte Register (BKA3M) .............................................. 334
7.20.4.9 Trigger 3 Address High Byte Register (BKA3H) ................................................. 334
7.21 Parallel Port (PP) ....................................................................................................................... 335
7.21.1 Overview ....................................................................................................................... 335
7.21.2 Features ........................................................................................................................ 335
7.21.3 Functional Description ................................................................................................... 335
7.21.3.1 KBS Connection with Parallel Port Connector .................................................... 335
7.21.3.2 In-System Programming Operation .................................................................... 335
8. Register List ......................................................................................................................................... 337
9. DC Characteristics ............................................................................................................................... 349
10. AC Characteristics................................................................................................................................ 351
11. Analog Device Characteristics .............................................................................................................. 363
12. Package Information............................................................................................................................. 365
13. Ordering Information............................................................................................................................. 369
14. Top Marking Information....................................................................................................................... 371
FIGURES
Figure 3-1. Host/Flash and EC/Flash Mapping (General) ............................................................................... 5
Figure 3-2. Host/Flash and EC/Flash Mapping (Flash Size = 512k, EC Code = 64k, a specific example) ........ 6
Figure 3-3. EC 8032 Data/Code Memory Map ............................................................................................... 8
Figure 5-1. Power State Transitions ............................................................................................................. 25
Figure 5-2. Clock Tree ................................................................................................................................. 33
Figure 5-3. LED connection ......................................................................................................................... 38
Figure 6-1. Host View Register Map via Index-Data Pair .............................................................................. 44
Figure 6-2. Program Flow Chart for PNPCFG .............................................................................................. 70
Figure 6-3. Scratch SRAM in Data Space .................................................................................................... 74
Figure 6-4. Follow Mode for Serial Flash (e.g. Fast Read Instruction)........................................................... 76
Figure 6-5. H2RAM-HLPC Mapping ............................................................................................................. 77
Figure 6-6. Wakeup Event and Gathering Scheme....................................................................................... 95
Figure 6-7. KBRST# Output Scheme ........................................................................................................... 97
Figure 6-8. GA20 Output Scheme ................................................................................................................ 98
Figure 6-9. KBC Host Interface Block Diagram........................................................................................... 107
Figure 6-10. IRQ Control in KBC Module ................................................................................................... 108
Figure 6-11. PMC Host Interface Block Diagram ........................................................................................ 113
Figure 6-12. EC Interrupt Request for PMC................................................................................................ 114
Figure 6-13. IRQ/SCI#/SMI# Control in PMC Compatible Mode ................................................................. 115
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IT8502E/F/G V0.7.7
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