OV5017 View Datasheet(PDF) - Omnivison Technologies

Part Name

Description

Manufacturer

OV5017

Single chip 1/4 video image sensor

Omnivison Technologies 

OMNIVISION TECHNOLOGIES, Inc.

OV5017

Confidential Preliminary Product Specification

Table 1.Pin Descriptions (Continued)

Pin #

22

23

24, 25

26

27

28

29

30

31

32-39

40

41

42

43

44

45

47

48

Class Pin Name

Description

I

WEB

I

CSB

OD

XCLKI,

XCLKO

OD

HREF

OD

PCLK

OD

VSYNC

Bias DVDD

Bias DGND

Bias OGND

OD

D0-D7

Bias OVDD

Bias ZVDD

Bias VR2

Bias ZGND

Bias DEGND

Bias DEVDD

Bias VVDD

Q

AVO

Write enable input for the internal registers. When the chip is selected (CSB = 0),

external data is latched into the registers with the rising edge of WEB.

Chip select for the device. CSB = 0 selects the device.

Crystal oscillator in/out pins. Nominal clock frequency is 14.31MHz for CCIR 50 Hz

timing. The maximum pixel rate is limited to one half of the clock frequency. To

connect an external clock to XCLKI, leave XCLKO open.

Horizontal timing reference output. Asserted high during every valid line for the

duration of the valid window width. The window sizing function affects the number

of valid lines in a frame as well as the number of valid pixels in a line. HREF and

status(1), are identical valid pixel timing information.

Pixel clock output. Defaulted to be a continuous clock. Can be programmed via the

internal register to be on during the valid pixel window only. Video data at output

bus (D0-D7) is updated with the rising edge of PCLK and is guaranteed to be valid

at the falling edge of PCLK.

Vertical timing reference output. It is high once per frame for the duration of the

vertical sync period. VSYNC and status (2) are identical vertical sync timing

information.

Digital power (+5V) connection.

Digital ground. Connect to supply common

Digital output ground. Connect to supply common

Bi-directional data bus for video output data and internal register read/write

operations.

Digital output power (+5V/+3.3V) connection.

Analog power (+5V) connection.

Internal reference voltage. Requires a 0.1uF external capacitor to AGND.

Analog ground. Connect to supply common.

Decoder ground. Connect to supply common.

Decoder power (+5V) connection.

Video output power (+5V) connection.

Composite video output. It is capable of driving 150 Ω load, Vp-p is 2.0 V.

Pin Type and Default Level:

I: digital input, floating, I-1: digital input, with 100k pull up, I-0: digital input, with 100k pull down, OD: digital CMOS level output, OA: analog

CMOS, level output, XI/XO: xtal IO, K: analog input, Q: 75Ω output, FT: factory test, Bias: power supply bias

October 20, 1997

Version 1.6

3

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