SSD1820A View Datasheet(PDF) - Solomon Systech

Part Name

Description

Manufacturer

SSD1820A

LCD Segment / Common Driver with Controller

Solomon Systech  

Oscillator Circuit

This module is an On-Chip low power RC oscillator circuitry

(Figure 7). The oscillator generates the clock for the DC-DC voltage

converter. This clock is also used in the Display Timing Generator.

enable

Oscillation Circuit

Oscillator enable

enable

Buffer

(CL)

OSC1

Internal pwell resistor

OSC2

Figure 7. Oscillator Circuitry

LCD Driving Voltage Generator and Regulator

This module generates the LCD voltage needed for display output.

It takes a single supply input and generate necessary bias voltages.

It consists of:

1. 2X, 3X, 4X, 5X and 6X DC-DC voltage converter

Please refer to application notes.

Please note that SSD1820A works up to 5X and SSD1820AT

works up to 4X only.

2. Voltage Regulator

Feedback gain control for initial LCD voltage. External resistors

are connected between VSS and VR, and between VR and VL6.

These resistors are chosen to give the desired VL6 according to

the following equation:

VL 6 = (1 + R 2 ) × Vcon ×G

R1

Vcon = (1 − 63 − α ) × V ref

210

where Vref is the internally generated reference voltage with a

known R1 and R 2. Typical value for Vref is 2.1V

R1 is the resistance of the resistor between VSS and VR.

R2 is the resistance of the resistors between VR and V L6.

α is the software contrast level from 0 to 63.

G = 1 if INTRS = VDD; REF = VDD

G = 0.84 if INTRS = VSS; REF = VDD

3. Bias Divider

If the output op-amp buffer option in Set Power Control Register

command is enabled, this circuit block will divide the regulator output

(V L6) to give the LCD driving levels (VL2 - VL5).

A low power consumption circuit design in this bias divider saves

most of the display current comparing to traditional design.

Stablizing Capacitors (0.47~2uF) are required to be connected

between these voltage level pins (V L2 - V L5) and VSS. If the LCD panel

loading is heavy, capacitors and four additional resistors are suggest-

ed to add to the application circuit as follows:

SSD1820A/21 Series

V SS

V L2

VL3

VL4

VL5

VL6

RL

RL

RL

RL

C2

C2

C2

C2

C2

VSS

Remarks: 1. C2 = 0.47 ~ 2.0uF

2. RL = 100K ~ 1M

Connections for heavy loading applications

4. Contrast Control

Software control of 64 voltage levels of LCD voltage.

5. Bias Ratio Selection circuitry

Software control of 1/ 4 to 1/10 bias ratio to match the characteris-

tic of LCD panel.

Note: SSD1820A has 1/4 to 1/9 bias only.

6. Self adjust temperature compensation circuitry

Provide 2 different compensation grade selections to satisfy the

various liquid crystal temperature grades. The grading can be

selected by software control. Defaulted temperature coefficient

(TC) value is -0.05% /oC for SSD1820A and -0.07%/oC for

SSD1821 .

193/209 Bit Latch

A register carries the display signal information. In 128 X 65/81 dis-

plamode. Data will be fed to the HV-buffer Cell and level-shifted to the

required level.

Level Selector

Level Selector is a control of the display synchronization. Display

voltage can be separated into two sets and used with different

cycles. Synchronization is important since it selects the required LCD

voltage level to the HV Buffer Cell, which in turn outputs the COM or

SEG LCD waveform.

SOLOMON

REV 1.4 SSD1820A/21

01/03

15

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