SSD1809T View Datasheet(PDF) - Solomon Systech
Part Name
Description
Manufacturer
SSD1809T Datasheet PDF : 27 Pages
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OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER
Description of Block Diagram Module
Command Decoder and Command Interface
This module determines whether the input data is interpreted as
data or command. Data is directed to this module based upon the
input of the D/ C pin. If D/C is high, data is written to Graphic Display
Data RAM (GDDRAM). If D/C is low, the input at SDA/D0-D7 is inter-
preted as a Command and it will be decoded and written to the corre-
sponding command register.
Reset is of the same function as Power ON Reset (POR). Once
RES receives a negative reset pulse of minimium 1µs, all internal cir-
cuit will be back to its initial status.
MPU 6800-series Parallel Interface
The parallel interface consists of 8 bi-directional data pins (D0-D7),
R/W, D/C, CE, and CLK. R/W input High indicates a read operation
from the Graphic Display Data RAM (GDDRAM) or the status regis-
ter.R /W input Low indicates a write operation to Display Data RAM or
Internal Command Registers depending on the status of D/C input.
The chip is enabled when the CE is low and the CLK input serves as
data latch signal (clock). Refer to Figure 2 showing timing character-
istics for 6800-series parallel interface.
MPU 80-Series Parallel Interface
The parallel interface consists of 8 bi-directional data pins (D0-D7),
RD, WR, D/C, and CE . RD input serves as data read latch signal
(clock) provided that CE is low. WR input serves as data write latch
signal(clock) provided that CE is low. Whether it is display data or
command register write is controlled by D/C. Refer to Figure 3 show-
ing timing characteristics for 80-series parallel interface.
MPU Serial Peripheral Interface
The serial interface consists of serial clock SCK, serial data SDA,
D/C, and CE. The chip is enabled when CE is low and SDA is shifted
into a 8-bit shift register on every falling edge of SCK and data are
transferred serially with MSB first and LSB last. D/C is sampled on
every first clock of each byte cycle and the information is interpreted
as Display Data or Command accordingly.
The eight bits information from SDA pin are stored in a buffer shift
register. After the next byte information from SDA pin is written into
the buffer, the original contents in the buffer will be sent to Display
Data RAM or Command Register. A No-Operation (01101000) com-
mand could be written to push the last information in the buffer into
Display RAM or Command Register.
The first bit after the CE pin falling edge or the RES pin rising edge
is always interpreted as MSB.
Refer to Figure 4 showing timing characteristics for Serial Periph-
eral Interface.
Selection of Interface
Selection of the desired interface is done by putting P/S and 68/80
either high or low as shown in the following table:-
PIN
6800-Series 80-Series
SPI
P/S
68/80
High
High
High
Low
Low
High/Low
Column address 00H
(or column address 9FH)
Column address 9FH
(or column address 00H)
Row 0
Page 1
Page 2
LSB
MSB
LSB
MSB
COM0
(COM63)
Page 8
Row 63
Row 64 Page 9
LSB
MSB
LSB
COM63
(COM0)
COM64
SSD1809
12
REV1.3
03/02
Note : The configuration in parentheses represent the remapping of Rows and Columns
Figure 5 : Graphic Display Data RAM (GDDRAM) Address Map
SOLOMON
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