SSD1809T View Datasheet(PDF) - Solomon Systech

Part Name

Description

Manufacturer

SSD1809T

LCD Segment / Common Driver With Controller

Solomon Systech  

Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM holding the bit pattern

to be displayed. The size of the RAM is determined by number of

row times the number of column (160x65 = 10400 bits). Figure 5 is a

description of the GDDRAM address map. For mechanical flexibility,

re-mapping on both Segment and Common outputs are provided.

Display Timing Generator

This module is an on chip low power RC oscillator circuitry (Fig-

ure 6). The oscillator frequency can be selected in the range of

25kHz to 200kHz by external resistor. One can enable the circuitry

by software command. For external clock provided, feed the clock to

OSC2 and leave OSC1 open.

Internal Oscillator selected

enable1 enable2

Oscillation Circuit

OSC1

OSC2

Oscillator enable

enable

Buffer

SSD1809

External component

Feedback for internal oscillator

For external CLK input

Figure 6 : Oscillator Circuitry

LCD Driving Voltage Generator and Regulator

This module generates the LCD voltage needed for display output.

It takes a single supply input and generate necessary bias voltages.

It consists of :

1. 2X, 3X, 4X and 5X DC-DC Converter

To generate the VCC voltage. 2X, 3X and 4X DC-DC converter are

used for LCD panel which needs lower driving voltage for less

power consumption. 5X DC-DC converter is used for LCD panel

which needs higher driving voltage.

2. Voltage Regulator

Feedback gain control for initial LCD voltage. it can also be used

with external contrast control.

3. Voltage Divider

Divide the LCD display voltage (VLL2-V LL6) from the regulator out-

put. This is a low power consumption circuit which can save the

most display current compare with traditional resistor ladder

method.

4. Self adjust temperature compensation circuitry

Provide 2 different compensation grade selections to satisfy the

various liquid crystal temperature grades. The grading can be

selected by software control.

5. Contrast Control Block

Software control of 16 voltage levels of LCD voltage.

All blocks can be individually turned off if external voltage genera-

tor is employed.

65 Bit Latch / 160 Bit Latch

A 225 bit long register which carries the display signal information.

First 65 bits are Common driving signals and other 160 bits are Seg-

ment driving signals. Data will be input to the HV-buffer Cell for

bumping up to the required level.

Level Selector

Level Selector is a control of the display synchronization. Display

voltage can be separated into two sets and used with different

cycles. Synchronization is important since it selects the required LCD

voltage level to the HV Buffer Cell for output signal voltage pump.

HV Buffer Cell (Level Shifter)

HV Buffer Cell works as a level shifter which translates the low

voltage output signal to the required driving voltage. The output is

shifted out with an internal FRM clock which comes from the Display

Timing Generator. The voltage levels are given by the level selector

which is synchronized with the internal M signal.

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

SOLOMON

Figure 7a : LCD Display Example “0”

REV 1.3 SSD1809

03/02

13

Share Link: