AT89S4D12-12JC View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT89S4D12-12JC

8-Bit Microcontroller with 132K Bytes Flash Data Memory

Atmel Corporation 

Table 4. SPSR—SPI Status Register

SPCR Address = AAH

Reset Value = 000X 0000B

SPIF

WCOL

—

—

—

—

—

—

Bit

7

6

5

4

3

2

1

0

Symbol

SPIF

WCOL

Table 5. SPDR—SPI Data Register

SPDR Address = 86H

Function

SPI Interrupt Flag. When a serial transfer is complete, the SPIF bit is set and an

interrupt is generated if SPIE = 1. The SPIF bit is cleared by reading the SPI status

register with SPIF and WCOL bits set, and then accessing the SPI data register.

Write Collision Flag. The WCOL bit is set if the SPI data register is written during a data

transfer. During data transfer, the result of reading the SPDR register may be incorrect,

and writing to it has no effect. The WCOL bit (and the SPIF bit) are cleared by reading

the SPI status register with SPIF and WCOL set, and then accessing the SPI data

register.

Reset Value = unchanged

SPD7

Bit

7

SPD6

6

SPD5

5

SPD4

4

SPD3

3

SPD2

2

SPD1

1

SPD0

0

Data Memory—Flash and RAM

The AT89S4D12 implements 128K bytes of on-chip Flash

for data storage and 256 bytes of RAM. The upper 128

bytes of RAM occupy a parallel space to the Special Func-

tion Registers. That means the upper 128 bytes have the

same addresses as the SFR space but are physically sepa-

rate from SFR space.

When an instruction accesses an internal location above

address 7FH, the address mode used in the instruction

specifies whether the CPU accesses the upper 128-bytes

of RAM or the SFR space. Instructions that use direct

addressing access SFR space.

For example, the following direct addressing instruction

accesses the SFR at location 086H (which is SPDR).

MOV 086H, #data

Instructions that use indirect addressing access the upper

128 bytes of RAM. For example, the following indirect

addressing instruction, where R0 contains 086H, accesses

the data byte at address 086H, rather than SPDR (whose

address is 086H).

MOV @R0, #data

Note that stack operations are examples of indirect

addressing, so the upper 128 bytes of data RAM are avail-

able as stack space.

The MOVX instructions are used to access the Flash data

memory.

Flash write cycles are self-timed and typically take 5 ms per

128-byte page. The progress of Flash write can be moni-

tored by reading the RDY/BSY bit (read-only) in SFR

MCON. RDY/BSY = 0 means programming is still in

progress and RDY/BSY = 1 means Flash write cycle is

completed and another write cycle can be initiated.

4-286

AT89S4D12

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